HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 65
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HSDC-JAKIT1W2/DB
Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r
Datasheets
1.ADC1413D125HNC15.pdf
(43 pages)
2.DAC1408D650HNC15.pdf
(98 pages)
3.HSDC-JAKIT1W2DB.pdf
(2 pages)
4.HSDC-JAKIT1W2DB.pdf
(2 pages)
5.HSDC-JAKIT1W2DB.pdf
(3 pages)
Specifications of HSDC-JAKIT1W2/DB
Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
NXP Semiconductors
Table 96.
Table 97.
Table 98.
Table 99.
Table 100. INIT_SCR_S7T1_LN2 register (address 16h) bit description
Table 101. INIT_SCR_S15T8_LN3 register (address 17h) bit description
Table 102. INIT_SCR_S7T1_LN3 register (address 18h) bit description
Table 103. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description
Table 104. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description
DAC1408D650
Product data sheet
Bit
6 to 0
Bit
7 to 0
Bit
6 to 0
Bit
7 to 0
Bit
6 to 0
Bit
7 to 0
Bit
6 to 0
Bit
7 to 4
3 to 0
Bit
7 to 4
3 to 0
Symbol
INIT_VALUE_S7_S1_LN0[6:0]
Symbol
INIT_VALUE_S15_S8_LN1[7:0]
Symbol
INIT_VALUE_S7_S1_LN1[6:0]
Symbol
INIT_VALUE_S15_S8_LN2[7:0]
Symbol
INIT_VALUE_S7_S1_LN2[6:0]
Symbol
INIT_VALUE_S15_S8_LN3[7:0]
Symbol
INIT_VALUE_S7_S1_LN3[6:0]
Symbol
INIT_ILA_BUFPTR_LN1[3:0]
INIT_ILA_BUFPTR_LN0[3:0]
Symbol
INIT_ILA_BUFPTR_LN3[3:0]
INIT_ILA_BUFPTR_LN2[3:0]
INIT_SCR_S7T1_LN0 (address 12h) bit description
INIT_SCR_S15T8_LN1 register (address 13h) bit description
INIT_SCR_S7T1_LN1 register (address 14h) bit description
INIT_SCR_S15T8_LN2 register (address 15h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
R/W
Access
R/W
R/W
Value
00h
Value
Value
00h
Value
00h
Value
00h
Value
00h
Value
00h
Value
8h
8h
Value
8h
8h
00h
2, 4 or 8 interpolating DAC with JESD204A
Description
initialization value for lane 0 descrambler bits s7 : s1
Description
s15 : s8
Description
initialization value for lane 1 descrambler bits s7 : s1
Description
initialization value for lane 2 descrambler bits
s15 : s8
Description
initialization value for lane 2 descrambler bits s7 : s1
Description
initialization value for lane 3 descrambler bits
s15 : s8
Description
initialization value for lane 3 descrambler bits s7 : s1
Description
initialization value for lane 1 ILA buffer pointer
initialization value for lane 0 ILA buffer pointer
Description
initialization value for lane 3 ILA buffer pointer
initialization value for lane 2 ILA buffer pointer
initialization value for lane 1 descrambler bits
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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