HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 73

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 124. INTR_MISC_ENA register (address 0Fh) bit description
Default settings are shown highlighted.
Table 125. FLAG_CNT_LSB_LN0 register (address 10h) bit description
Default settings are shown highlighted.
Table 126. FLAG_CNT_MSB_LN0 register (address 11h) bit description
Default settings are shown highlighted.
Table 127. FLAG_CNT_LSB_LN1 register (address 12h) bit description
Default settings are shown highlighted.
Table 128. FLAG_CNT_MSB_LN1 register (address 13h) bit description
Default settings are shown highlighted.
Table 129. FLAG_CNT_LSB_LN2 register (address 14h) bit description
Default settings are shown highlighted.
Table 130. FLAG_CNT_MSB_LN2 register (address 15h) bit description
Default settings are shown highlighted.
Table 131. FLAG_CNT_LSB_LN3 register (address 16h) bit description
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Symbol
INTR_ENA_CS_INIT_LN3
INTR_ENA_CS_INIT_LN2
INTR_ENA_CS_INIT_LN1
INTR_ENA_CS_INIT_LN0
INTR_ENA_BUF_ERR_LN3
INTR_ENA_BUF_ERR_LN2
INTR_ENA_BUF_ERR_LN1
INTR_ENA_BUF_ERR_LN0
Symbol
FLAG_CNT_LN0[7:0]
Symbol
FLAG_CNT_LN0[15:8]
Symbol
FLAG_CNT_LN1[7:0]
Symbol
FLAG_CNT_LN1[15:8]
Symbol
FLAG_CNT_LN2[7:0]
Symbol
FLAG_CNT_LN2[15:8]
Symbol
FLAG_CNT_LN3[7:0]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R
Access
R
Access
R
Access
R
Access
R
Access
R
Access
R
Value
0
0
0
0
0
0
0
0
Value
Value
Value
Value
Value
Value
Value
-
-
-
-
-
-
-
2, 4 or 8 interpolating DAC with JESD204A
Description
intr_misc in case cs_state_ln3 = cs_init
intr_misc in case cs_state_ln2 = cs_init
intr_misc in case cs_state_ln1 = cs_init
intr_misc in case cs_state_ln0 = cs_init
generate interrupt if ILA_BUF_ERR_LN3 = 1
generate interrupt if ILA_BUF_ERR_LN2 = 1
generate interrupt if ILA_BUF_ERR_LN1 = 1
generate interrupt if ILA_BUF_ERR_LN0 = 1
Description
Description
Description
Description
Description
Description
Description
LSBs of flag_counter lane 0
MSBs of flag_counter lane 0
LSBs of flag_counter lane 1
MSBs of flag_counter lane 1
LSBs of flag_counter lane 2
MSBs of flag_counter lane 2
LSBs of flag_counter lane 3
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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