HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 37

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
10.13.4 Phase correction
10.15.1 Register description
10.15.2 Detailed descriptions of registers
10.14 Power and grounding
10.15 Configuration interface
The Analog Quadrature Modulator which follows the DACs may have a phase imbalance
which results in undesired sidebands. By adjusting the phase between the I and Q
channels, the spur can be reduced.
Without compensation the I and Q have a phase difference of  / 2 (90). The registers
PHASECORR_CNTRL0 and PHASECORR_CNTRL1 located in register page 0 allow a
phase variation from 75.7 to 104.3. The two registers define a signed value that ranges
from 512 to +511. The resulting phase compensation (in radians) is given by the
equation: PHASE_CORR[9:0] / 2048.
The power supplies should be decoupled with the following ground pins to optimize the
decoupling:
DAC1408D650 implements indirect addressing using a page access method. The
page-address is located at address 0x1F and is by default 0x00, which selects page 0 as
the default page. For example, to access registers which configure the deserializer, one
must first activate page 4 by writing 0x04 to the page-address 0x1F.
The DAC1408D650 contains six different pages.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
The register information has been provided in page form accompanied by a detailed
description for each bit in the tables following the register allocation map of each page.
•
V
pin 32 with pin 31.
DDA(1V8)
: pin 38 with pin 37; pin 44 with pin 43; pin 11 with pin 12; pin 17 with pin 18;
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
2, 4 or 8 interpolating DAC with JESD204A
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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