HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 22

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HSDC-JAKIT1W2/DB

Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r

Specifications of HSDC-JAKIT1W2/DB

Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
NXP Semiconductors
DAC1408D650
Product data sheet
Fig 12. Frame assembly
b9
b9
b9
b9
b8
b8
b8
b8
b7
b7
b7
b7
b6
b6
b6
b6
SERIAL CLOCK
3.125 GHz
b5
b5
b5
b5
b4
b4
b4
b4
b3
b3
b3
b3
b2
b2
b2
b2
b1
b1
b1
b1
b0
b0
b0
b0
/10
/10
/10
/10
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
encoded
encoded
encoded
encoded
octet
octet
octet
octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CHARACTER CLOCK
312.5 MHz
lane 0
lane 1
lane 2
lane 3
scrambled
scrambled
scrambled
scrambled
octet
octet
octet
octet
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
2, 4 or 8 interpolating DAC with JESD204A
ON/OFF
ON/OFF
ON/OFF
ON/OFF
FRAME CLOCK
312.5 MHz
F = 1 byte
byte 0
byte 1
byte 2
byte 3
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
T
T
T
T
DAC1408D650
/F
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
© NXP B.V. 2010. All rights reserved.
M = 2 converters
DAC0
DAC1
001aak164
22 of 98

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