HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 23

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
Fig 13. SPI protocol
RESET_N
(optional)
SCS_N
SCLK
SDIO
SDO
R/W indicates the mode access, (see
10.3.1 Protocol description
10.3 Serial Peripheral Interface (SPI)
R/W
The DAC1408D650 serial interface is a synchronous serial communication port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that define the operating modes of the chip in both Write mode and Read mode.
This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pin, input and output port respectively). In both
configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with two bytes to five bytes, depending on the content of the
instruction byte (see
Table 7.
In
byte.
Table 8.
A[4:0] indicates which register is being addressed. In the case of a multiple transfer, this
address points to the first register to be accessed. The address is then internally
decreased after each following data phase.
R/W
N1
0
0
1
1
0
1
N1
Table 8
N0
below, N1 and N0 indicate the number of bytes transferred after the instruction
Read or Write mode access description
Number of bytes to be transferred
A4
All information provided in this document is subject to legal disclaimers.
A3
Table
Description
Write mode operation
Read mode operation
Table
N0
0
1
0
1
Rev. 4 — 26 November 2010
7).
A2
8).
A1
A0
D7
D7
2, 4 or 8 interpolating DAC with JESD204A
Number of bytes transferred
1
2
3
4
D6
D6
D5
D5
D4
D4
DAC1408D650
D3
D3
D2
D2
© NXP B.V. 2010. All rights reserved.
D1
D1
D0
D0
001aaj812
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