HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 70

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 109. ILA_MON_1_0 register (address 00h) bit description
Default settings are shown highlighted.
Table 110. ILA_MON_3_2 register (address 01h) bit description
Default settings are shown highlighted.
Table 111. ILA_BUF_ERR register (address 02h) bit description
Default settings are shown highlighted.
Table 112. CA_MON register (address 03h) bit description
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7 to 4
3 to 0
Bit
7 to 4
3 to 0
Bit
3
2
1
0
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Symbol
ILA_MON_LN1[3:0]
ILA_MON_LN0[3:0]
Symbol
ILA_MON_LN3[3:0]
ILA_MON_LN2[3:0]
Symbol
ILA_BUF_ERR_LN3
ILA_BUF_ERR_LN2
ILA_BUF_ERR_LN1
ILA_BUF_ERR_LN0
Symbol
CA_MON_LN3[1:0]
CA_MON_LN2[1:0]
CA_MON_LN1[1:0]
CA_MON_LN0[1:0]
10.15.2.10 Page 5 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 108
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R
R
Access
R
R
Access
R
R
R
R
Access
R
R
R
R
for a register overview and their default values. In the following
Value
-
-
Value
-
-
Value
0
1
0
1
0
1
0
1
Value
-
-
-
-
2, 4 or 8 interpolating DAC with JESD204A
Description
ila_buf_ln1 pointer
ila_buf_ln0 pointer
Description
ila_buf_ln3 pointer
ila_buf_ln2 pointer
Description
lane 3 ila buffer error
lane 2 ila buffer error
lane 1 ila buffer error
lane 0 ila buffer error
Description
clock alignment phase monitor lane 3
clock alignment phase monitor lane 2
clock alignment phase monitor lane 1
clock alignment phase monitor lane 0
ila_buf_ln3 pointer is in range
ila_buf_ln3 pointer is out of range
ila_buf_ln2 pointer is in range
ila_buf_ln2 pointer is out of range
ila_buf_ln1 pointer is in range
ila_buf_ln1 pointer is out of range
ila_buf_ln0 pointer is in range
ila_buf_ln0 pointer is out of range
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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