HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 63

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 91.
Default settings are shown highlighted.
Table 92.
DAC1408D650
Product data sheet
Bit
7 to 5
4
3 to 0
Bit
3
2
1
0
Symbol
SEL_RE_INIT[2:0]
SYNC_POL
SEL_SYNC[3:0]
Symbol
POL_LN3
POL_LN2
POL_LN1
POL_LN0
SYNCOUT_MODE register (address 0Ch) bit description
LANE_POLARITY register (address 0Dh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Value
000
001
010
011
100
101
110
111
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
other
Value
0
1
0
1
0
1
0
1
2, 4 or 8 interpolating DAC with JESD204A
Description
reinitialization mode
synchronization polarity
synchronization mode
Description
lane 3 data polarity
lane 2 data polarity
lane 1 data polarity
lane 0 data polarity
i_re_init when 1 of the lane_rst's is active
i_re_init when rst_ln0 or rst_ln1 is active
i_re_init when rst_ln2 or rst_ln3 is active
i_re_init when rst_ln0 is active
i_re_init when rst_ln1 is active
i_re_init when rst_ln2 is active
i_re_init when rst_ln3 is active
i_re_init remains '0'
sync_out is active when LOW
sync_out is active when HIGH
sync when one of the four lane_syncs is active
sync when all four lane_syncs are active
sync when sync_ln0 or sync_ln1 is active
sync when both sync_ln0 and sync_ln1 are active
sync when sync_ln2 or sync_ln3 is active
sync when both sync_ln2 and sync_ln3 are active
sync when sync_ln0 is active
sync when sync_ln1 is active
sync when sync_ln2 is active
sync when sync_ln3 is active
sync remains fixed '1'
sync remains fixed '0'
no action
invert all data bits of lane 3
no action
invert all data bits of lane 2
no action
invert all data bits of lane 1]
no action
invert all data bits of lane 0
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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