A2F200M3F-FGG484 Actel, A2F200M3F-FGG484 Datasheet - Page 109
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A2F200M3F-FGG484
Manufacturer Part Number
A2F200M3F-FGG484
Description
ACLA2F200M3F-FGG484 SMART FUSION MIX SIG
Manufacturer
Actel
Datasheet
1.A2F500M3B-1CSH484.pdf
(170 pages)
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4 – SmartFusion Programming
In-System Programming
SmartFusion devices have three separate flash areas that can be programmed:
There are essentially three methodologies for programming these areas:
Programming, whether ISP or IAP methodologies are employed, can be done in two ways:
In-System Programming is performed with the aid of external JTAG programming hardware.
describes the JTAG programming hardware that will program a SmartFusion device and
defines the JTAG pins that provide the interface for the programming hardware.
Table 4-1 • Supported JTAG Programming Hardware
Table 4-2 • SmartFusion JTAG Pin Descriptions
The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAG SEL is
asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset
state (logic 0), as depicted in
Dongle
FlashPro3/4
ULINK Pro
ULINK2
IAR J-Link
Notes:
1. SWD = ARM Serial Wire Debug
2. SWV = ARM Serial Wire Viewer
Pin Name
JTAGSEL
TRSTB
TCK
TMS
TDI
TDO
1. The FPGA fabric
2. The embedded nonvolatile memories (eNVMs)
3. The embedded flash ROM (eFROM)
1. In-system programming (ISP)
2. In-application programming (IAP)—only the FPGA Fabric and the eNVM
3. Pre-programming (non-ISP)
1. Securely using the on chip AES decryption logic
2. In plain text
Source
ARM Cortex-M3 or FPGA test access port (TAP) controller selection
Test reset bar
Test clock
Test mode select
Test data input
Test data output
Actel
Keil
Keil
IAR
Figure
JTAG
Yes
Yes
Yes
Yes
4-1. Users should tie the JTAGSEL pin high externally.
R e v i s i o n 3
SWD
Yes
Yes
Yes
No
1
Description
SWV
Yes
Yes
Yes
No
2
Program
FPGA
Yes
Yes
Yes
Yes
Program
eFROM
Yes
Yes
Yes
Yes
Program
Table 4-1
Table 4-2
eNVM
Yes
Yes
Yes
Yes
4 -5
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