M29W320DT70N6E Micron Technology Inc, M29W320DT70N6E Datasheet - Page 13

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M29W320DT70N6E

Manufacturer Part Number
M29W320DT70N6E
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of M29W320DT70N6E

Cell Type
NOR
Density
32Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Top
Address Bus
22/21Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6/12V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
4M/2M
Supply Current
10mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant

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2.7
2.8
2.9
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
V
The V
use an external high voltage power supply to reduce the time required for Unlock Bypass
Program operations. The Write Protect function provides a hardware method of protecting
the 16 Kbyte Boot Block. The V
When V
and Erase operations in this block are ignored while V
When V
of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the
16 Kbyte Boot Block unless the block is protected using Block Protection.
When V
Bypass mode. When V
During Unlock Bypass Program operations the memory draws I
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from V
t
Never raise V
memory may be left in an indeterminate state.
A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, I
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if V
even if RP is at V
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t
ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section,
Holding RP at V
and Erase operations on all blocks will be possible. The transition from V
slower than t
VHVPP
PP/
PP
PLPX
Write Protect (V
, see
PP
PP
PP
/Write Protect pin provides two functions. The V
/Write Protect is Low, V
/Write Protect is High, V
/Write Protect is raised to V
. After Reset/Block Temporary Unprotect goes High, V
Figure
PHPHH
PP
PP
/WP is at V
/Write Protect to V
ID
ID
will temporarily unprotect the protected Blocks in the memory. Program
13.
.
.
PP
/Write Protect returns to V
IL
, then the 16 KByte outermost boot block will remain protect
PP
PP
/WP)
IL
/Write Protect pin must not be left floating or unconnected.
PP
IH
, the memory protects the 16 Kbyte Boot Block; Program
, the memory reverts to the previous protection status
Table 15
from any mode except Read mode, otherwise the
PP
IH
the memory automatically enters the Unlock
to V
PP
and
and from V
Figure
IH
PHEL
or V
PP
PP
PP
/Write Protect is Low.
/Write Protect pin and the V
or t
12, for more details.
IL
function allows the memory to
normal operation resumes.
PP
RHEL
PP
to V
IH
, whichever occurs last.
from the pin to supply the
, the memory will be
IH
must be slower than
IH
to V
ID
PP
must be
.
IL
, for at
SS
13/56

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