IDT82V3002APV IDT, Integrated Device Technology Inc, IDT82V3002APV Datasheet
IDT82V3002APV
Specifications of IDT82V3002APV
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IDT82V3002APV Summary of contents
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FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra- tum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s inter- faces • Supports ITU-T G.812 Type IV clocks ...
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IDT82V3002A FUNCTIONAL BLOCK DIAGRAM OSCi OSCo OSC Fref0 Reference Fref1 Input Switch IN_sel FLOCK Reference MON_out Input Monitor RST Invalid Input Signal Detection TDI TMS JTAG TRST TCK TDO TIE_en FUNCTIONAL BLOCK DIAGRAM TCLR DDD SS ...
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IDT82V3002A PIN CONFIGURATION........................................................................................................................... 6 2 PIN DESCRIPTION ........................................................................................................................................................ 7 3 FUNCTIONAL DESCRIPTION..................................................................................................................................... 10 3.1 State Control Circuit............................................................................................................................................. 10 3.1.1 Normal Mode ............................................................................................................................................11 3.1.2 Fast Lock Mode ........................................................................................................................................ 11 3.1.3 Holdover Mode ......................................................................................................................................... 11 3.1.4 Freerun Mode ........................................................................................................................................... 12 3.2 ...
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Figure - 1 Block Diagram .................................................................................................................................................. 2 Figure - 2 IDT82V3002A SSOP56 Package Pin Assignment........................................................................................... 6 Figure - 3 State Control Block......................................................................................................................................... 10 Figure - 4 State Control Diagram.................................................................................................................................... 11 Figure - 5 TIE Control Circuit Diagram ........................................................................................................................... 13 Figure ...
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Table - 1 Pin Description .................................................................................................................................................. 7 Table - 2 Operating Modes and Status...........................................................................................................................10 Table - 3 Input Reference Frequency Selection ............................................................................................................. 12 Table - 4 Reference Input Switch Control....................................................................................................................... 12 Table - 5 Absolute Maximum Ratings**.......................................................................................................................... 20 Table - ...
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IDT82V3002A 1 IDT82V3002A PIN CONFIGURATION MODE_sel0 MODE_sel1 MON_out IDT82V3002A PIN CONFIGURATION TCLR 4 RST 5 Fref0 6 Fref1 F_sel0 9 F_sel1 10 IN_sel DDD 14 C6o 15 C1.5o ...
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IDT82V3002A 2 PIN DESCRIPTION Table - 1 Pin Description Pin Name Type Number 12, 18, 27, Ground. V Power SS 38 All V 3.3 V Analog Power Supply. V Power 37, 48 DDA Refer to 3.3 V ...
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IDT82V3002A Table - 1 Pin Description (Continued) Pin Name Type Number Holdover Indicator. HOLDOVER (CMOS This output goes to a logic high whenever the DPLL goes into Holdover Mode. Normal Indicator. NORMAL (CMOS This output goes ...
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IDT82V3002A Table - 1 Pin Description (Continued) Pin Name Type Number Test Reset. TRST I 30 Asynchronously initializes the JTAG TAP controller by putting it in Test-Logic-Reset state. This pin is internally pulled DDD Test Clock. TCK ...
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IDT82V3002A 3 FUNCTIONAL DESCRIPTION The IDT82V3002A is a WAN PLL with dual reference inputs, providing timing (clock) and synchronization (framing) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. See Figure - 1. The detail is ...
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IDT82V3002A S1 Normal Mode_sel1 = 0 Mode_sel0 = 0 * Note: After reset, Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'. 3.1.1 NORMAL MODE Normal Mode is typically used when a slave clock source synchronized to the ...
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IDT82V3002A corresponds to the worst case of 18 frame (125 µs per frame) slips in 24 hours. This meets AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24 hours). The HOLDOVER pin will ...
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IDT82V3002A TIE_en IN_sel Fref0 Select Circuit Fref1 Feedback signal The TIE Control Block will work under the control of the Step Generation circuit when it is enabled manually or automatically (by the TIE_en pin or TIE auto-enable logic generated by ...
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IDT82V3002A Fref0 Fref1 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s Figure - 7 Reference Switch ...
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IDT82V3002A 3.7 DPLL BLOCK As shown in Figure - 8, the DPLL Block consists of a Phase Detector, Fraction_T1 Fraction_C6 Loop Filter 3.7.1 PHASE DETECTOR (PHD) In Normal Mode, the Phase Detector compares the virtual reference signal from the TIE ...
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IDT82V3002A respectively. 3.7.5 DIGITAL CONTROL OSCILLATOR (DCO) In Normal Mode, the DCO receives three limited and filtered signals from Loop Filter or Fraction blocks. Based on the received signals, the DCO generates three digital outputs, 25.248 MHz, 32.768 MHz and ...
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IDT82V3002A 3.11 POWER SUPPLY FILTERING TECHNIQUES To achieve optimum jitter performance, power supply filtering is required to minimize supply noise modulation of the output clocks. The common sources of power supply noise are switching power supplies and the high switching ...
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IDT82V3002A 4 MEASURES OF MANCE The following are some synchronizer performance indicators and their corresponding definitions. 4.1 INTRINSIC JITTER Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output measured by applying ...
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IDT82V3002A 4.11 PHASE CONTINUITY Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of ...
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IDT82V3002A 5 TEST SPECIFICATIONS Table - 5 Absolute Maximum Ratings** Rating Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent ...
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IDT82V3002A 5.1 AC ELECTRICAL CHARACTERISTICS Table - 8 Performance** Description Freerun Mode accuracy with OSCi ppm Freerun Mode accuracy with OSCi at : ±32 ppm Freerun Mode accuracy with OSCi at : ±100 ppm Holdover Mode accuracy ...
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IDT82V3002A Table - 10 C1.5o (1.544 MHz) Intrinsic Jitter Filtered Description Intrinsic jitter ( 100 kHz filter) Intrinsic jitter ( kHz filter) Intrinsic jitter (8 kHz to 40 kHz filter) Intrinsic jitter ( ...
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IDT82V3002A Table - 14 2.048 MHz Input to 2.048 MHz Output Jitter Transfer Description Jitter at output for 1 Hz@3.00 UIpp input Jitter at output for 1 Hz@3.00 UIpp input with 100 Hz filter Jitter at output ...
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IDT82V3002A Table - 17 2.048 MHz Input Jitter Tolerance Description Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input ...
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IDT82V3002A 6 TIMING CHARACTERISTICS Table - 18 Timing Parameter Measurement Voltage Levels Parameter Rise and Fall Threshold Voltage High HM V Rise and Fall Threshold Voltage Low LM Notes: 1. Voltages are with respect to ground (V ...
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IDT82V3002A Table - 19 Input / Output Timing (Continued) Parameter Description t C2o pulse width high or low C2W t C4o pulse width high or low C4W t C8o pulse width high or low C8W t C16o pulse width high ...
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IDT82V3002A F8o F0o F16o F32o C32o C16o C8o t C4W C4o C2o t C6W C6o C3o C1.5o TIMING CHARACTERISTICS t F0WL t F16WL t F16S t F32WL t F32S t C32WH t C16WL t t C8W C8W t C4W t ...
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IDT82V3002A F8o C2o RSP TSP F8o MODE_sel0 MODE_sel1 TIE_en IN_sel TIMING CHARACTERISTICS t RSPD t TSPW t TSPD Figure - 14 Output Timing Figure - 15 Input Control Setup and Hold Timing 28 WAN PLL ...
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IDT82V3002A 7 ORDERING INFORMATION XXXXXXXX Device Type Package DATASHEET DOCUMENT HISTORY 10/22/2003 pgs. 7, 24, 25 11/18/2004 pgs 05/24/2006 pgs CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is ...