IDT82V3002APV IDT, Integrated Device Technology Inc, IDT82V3002APV Datasheet - Page 13

• Manufacturer Part Number: IDT82V3002APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3002APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Generation circuit when it is enabled manually or automatically (by the
TIE_en pin or TIE auto-enable logic generated by the State Control
Circuit).
(current output feedback from the Frequency Select Circuit) by the
Measure Circuit. The phase difference between the input reference and
applying a logic low pulse to the TCLR pin. The reset pulse should be at
least 300 ns.
time periods and then turns back to Normal Mode, the TIE Control
Circuit should not be enabled. This will prevent undesired accumulated
phase change between the input and output.
FUNCTIONAL DESCRIPTION
IDT82V3002A
The TIE Control Block will work under the control of the Step
The selected reference signal is compared with the feedback signal
The phase difference in the Storage Circuit can be cleared by
When the IDT82V3002A primarily enters Holdover Mode for short
If the TIE Control Block is disabled manually or automatically during
Feedback
TIE_en
signal
IN_sel
Fref0
Fref1
Circuit
Select
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Fref0
Fref1
Figure - 6 Reference Switch with TIE Control Block Enabled
Fref
Figure - 5 TIE Control Circuit Diagram
Measure
Circuit
Step Generation
13
the feedback signal is sent to the Storage Circuit for TIE correction. The
Trigger Circuit generates a virtual reference with the phase corrected to
the same position as the previous reference according to the value
stored in the Storage Circuit. With this TIE correction mechanism, the
reference is switched without generating a step change in phase.
switch is performed with the TIE Control Block enabled.
the reference switching, the phase of the output signal will align with that
of the new reference. The phase slope is limited to 5 ns per 125 µs.
Figure - 7
with the TIE Control Block disabled.
Figure - 6
Storage
Circuit
TCLR
shows the phase transient resulting from a reference switch
shows the phase transient that would result if a reference
WAN PLL WITH DUAL REFERENCE INPUT
Output Clock
Input Clock
Trigger
Circuit
October 15, 2008
Reference
Virtual
Signal