MB91F376G Fujitsu Components, MB91F376G Datasheet - Page 109

• Manufacturer Part Number: MB91F376G
• Manufacturer: Fujitsu Components

Specifications of MB91F376G

• Lead Free Status / Rohs Status: Not Compliant

2. Boot ROM
(1) Chip initializations
(2) Check for bootcondition
(3) Bootstraploader
(4) Configuration register (F362 mode register F362MD)
The Boot ROM is a fixed start-up routine which is located at FF000
after every RST or INIT. The purpose of this ROM is to configure the device after a reset and to provide a simple
serial bootloader for programming the embedded Flash memories.
The Boot ROM contains three logical parts :
Immediately after each reset, the following settings will be made :
CS0 : 200000
CS7 : 100000
In addition, the Table-Base Register will be initialized to 1FFC00
(see TBCR) will be enabled.
After the chip initialization, the “Security-Vector” will be checked (Vector #66) . The purpose of this feature is to
disable the bootstraploader due to security reasons.
The RSRR (reset cause register) will be read and saved. If no power-on reset (external INITX input, RSRR =
0x80) is indicated, a branch to the user application will be initiated (Branch to 1F4000
If INITX was detected and the “Security-Vector” check okay, the following conditions must be met in order to
start the Bootstraploader :
Within a certain time, the start-up character “V” must be received via UART0 (9600, 8N1) . The time-out is set
to 200 ms.
If the Bootcondition was met, an acknowledge character “F” will be transmitted via UART0 to indicate that the
Bootloader is ready to accept commands. 4 different commands are possible :
This register is used to control which pins of the external bus interface are active, where the pins for the external
DMA channel are located and which I
Receive and write to a specified memory block
Dump the contents of a specified memory block
Initiate a “CALL” to a certain location
Re-dump a calculated checksum for verification
address
00001FE
Initial value
access
H
H
…2FFFFF
…10FFFF
H
ADRSWAP
bit 15
R/W
0
H
H
, 32 Bit Bus, 1 wait-state (default external access)
, 16 Bit Bus, 1 wait-state (CAN)
ASYMCLKT HIZ_D_A
bit 14
R/W
0
2
C module is used.
bit 13
R/W
0
HIZ_ECLK
bit 12
R/W
0
HIZ_D_23_16 HIZ_D_15_0
bit 11
R/W
0
H
H
(Reset entry) and will therefore be executed
(F361GA only) and the synchronous reset
MB91360G Series
bit 10
R/W
0
DMASWP
bit 9
R/W
0
H
) .
IICSEL
bit 8
R/W
0
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