MB91F376G Fujitsu Components, MB91F376G Datasheet - Page 158

• Manufacturer Part Number: MB91F376G
• Manufacturer: Fujitsu Components

Specifications of MB91F376G

• Lead Free Status / Rohs Status: Not Compliant

158
MB91360G Series
(3) Block diagram
(User Logic Bus)
External Bus
DLCR0 to 15,
DTR0 to 15,
BTR
CSR
CREG
IDR0 to 15,
RFWTR
ROVRR
TREQR
TCANR
RRTRR
TRTRR
BVALR
AMSR
AMR0
AMR1
RTEC
TIER
RIER
RCR
RAM
LEIR
TCR
NS1,0
HALT
PSC
TOE
RSJ
NIE
PR
PH
RS
TS
NT
CANCLK
CLKT
0
1
frequency division
RBFx, set
Node status change
TBFx,
Transmission complete
interrupt generation
TBFx, set, clear
RBFx, set
Prescaler 1 to 64
clear
RBFx, TBFx, set, clear
Reception complete
TBF
interrupt generation
interrupt generator
RAM address
generation
X
Acceptance
buffer x decision
IDSEL
Transmitting
Clock
Configuration
filter
change interrupt
RBF
Node status
Transmission
Receiving buffer x
Bit timing generation
completed
Reception
interrupt
complete
interrupt
X
, TBF
decision
RBF
TBF
Clock for CAN transmit/receive operation
Clock for External Bus Access
X
, RDLC, TDLC, IDSEL
X
X
control
Error
TDLC RDLC
counter
Data
BITER, STFER,
CRCER, FRMER,
ACKER
Transmitting/
Transmission
shift register
shift register
ARBLOST
sequencer
SYNC, TSEG1, TSEG2
receiving
RDLC
TQ (Operating clock)
Receive
FRMER
ACKER
TDLC
Acceptance
filter control
BITER
IDSEL
CRC generator/
CRCER
error check
generation
CRC
Acknowledgment
error check
Form error
Arbitration
machine
ARBLOST
Bit error
error check
state
Destuffing/
check
check
check
Bus
generation
generation
stuffing
Overload
generation
Stuffing
frame
frame
Error
ACK
STFER
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
Output
driver
PH1
Input
latch
RX
TX