MB91F376G Fujitsu Components, MB91F376G Datasheet - Page 143

• Manufacturer Part Number: MB91F376G
• Manufacturer: Fujitsu Components

Specifications of MB91F376G

• Lead Free Status / Rohs Status: Not Compliant

15. Clock Generation
(1) Register configuration
The MB91360G series generates internal operating clocks as follows :
Generation and control of each clock are explained below.
Some devices allow the operation of the RTC module based on a separate 32 kHz subclock. See the section
“27. Subclock” for more details.
RSRR : Reset source register, Watchdog timer control register
* : varies with reset factor
x : not initialized
** : After execution of the program in the internal boot ROM the reset source is visible
STCR
* : Valid only when this initialization is performed simultaneously with initialization by INITX : others same as INIT.
• Base clock generation : Device scales clock source input by 2 (X clock) or oscillates base clock with PLL to
• Generation of each internal clock : Device scales base clock to generate clocks supplied to each block
Initial Value (HSTX) *
address : 00000480
address : 00000481
Initial Value (INITX)
Initial Value (INITX)
Initial Value (RST)
After Boot ROM **
Initial Value (RST)
Initial Value (INIT)
Initial Value (INIT)
:
Standby control register
access
access
bit
bit
H
H
generate basic clock (PLL clock)
STOP
R/W
INIT
15
R
X
1
0
7
0
0
0
0
*
SLEEP
HSTB
R/W
14
R
X
0
0
6
0
0
0
0
*
WDOG
R/W
HIZ
13
R
X
X
0
0
5
1
1
1
*
ERST
SRST
R/W
12
R
X
0
0
4
1
1
1
1
*
SRST
OS1
R/W
11
R
X
X
X
0
0
3
0
1
*
OS0
R/W
10
⎯
⎯
⎯
⎯
⎯
X
X
MB91360G Series
0
2
0
1
OSCD2 OSCD1
WT1
R/W
R/W
X
9
0
0
0
0
1
1
1
1
WT0
R/W
R/W
8
0
0
0
0
0
1
1
1
X
(Continued)
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