PCF8576DT NXP Semiconductors, PCF8576DT Datasheet - Page 23

• Manufacturer Part Number: PCF8576DT
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 20
• Number Of Segments: 160
• Package Type: TSSOP
• Pin Count: 56
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 400KHz
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
PCF8576D_9
Product data sheet
7.16.5 I
7.16.6 Input filters
7.16.7 I
Acknowledgement on the I
The PCF8576D acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
subaddress.
In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally
tied to V
applications A0, A1 and A2 are tied to V
scheme such that no two devices with a common I
hardware subaddress.
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
The least significant bit of the slave address that a PCF8576D will respond to is defined by
the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to
a read access. Having two reserved slave addresses allows the following on the same
I
2
2
2
2
Fig 16. Acknowledgement of the I
•
C-bus slave address, on the transferred command data and on the hardware
C-bus:
•
•
C-bus controller
C-bus protocol
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Up to 16 PCF8576Ds for very large LCD applications
The use of two types of LCD multiplex drive.
2
C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8576D.
by transmitter
SS
data output
by receiver
data output
SCL from
which defines the hardware subaddress 0. In multiple device
master
2
condition
C-bus master receiver. The only data output from the PCF8576D are
START
Rev. 09 — 25 August 2009
S
2
C-bus is shown in
2
C-bus slave receiver. It does not initiate I
2
1
C-bus
SS
Universal LCD driver for low multiplex rates
or V
Figure
2
DD
in accordance with a binary coding
2
C-bus slave address have the same
16.
not acknowledge
acknowledge
8
PCF8576D
acknowledgement
clock pulse for
2
C-bus transfers or
© NXP B.V. 2009. All rights reserved.
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