LH28F320BFHE-PTTL60 Sharp Electronics, LH28F320BFHE-PTTL60 Datasheet
LH28F320BFHE-PTTL60
Specifications of LH28F320BFHE-PTTL60
Related parts for LH28F320BFHE-PTTL60
LH28F320BFHE-PTTL60 Summary of contents
Page 1
... P S RODUCT PECIFICATIONS LH28F320BFHE-PTTL60 ® Flash Memory 16M (2MB × 8) (Model No.: LHF32FB2) Spec No.: EL14Z048 Issue Date: December 20, 2002 Integrated Circuits Group ...
Page 2
...
Page 3
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered ...
Page 4
TSOP Pinout................................................. 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 7 Identifier Codes and OTP Address for Read Operation on ...
Page 5
... Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number. * ETOX is a trademark of Intel Corporation. LHF32FB2 LH28F320BFHE-PTTL60 32Mbit (2Mbit×16) Flexible Blocking Architecture • Eight 4K-word Parameter Blocks • ...
Page 6
WE# 11 RST WP#/ACC 14 RY/BY# ...
Page 7
... DEVICE POWER SUPPLY (2.7V-3.6V): With V V SUPPLY flash memory are inhibited. Device operations at invalid V CC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins ...
Page 8
Table 2. Simultaneous Operation Modes Allowed with Four Planes THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE Read Read PARTITION IS: Array ID/OTP Read Array X X Read ID/OTP X X Read Status X X Read ...
Page 9
BLOCK NUMBER ADDRESS RANGE 70 4K-WORD 69 4K-WORD 68 4K-WORD 67 4K-WORD 66 4K-WORD 65 4K-WORD 64 4K-WORD 63 4K-WORD 62 32K-WORD 61 32K-WORD 60 32K-WORD 59 32K-WORD 58 32K-WORD 57 32K-WORD 56 32K-WORD 55 32K-WORD 54 32K-WORD 53 ...
Page 10
Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Top Parameter Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration ...
Page 11
Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP Block Address Map for OTP Program LHF32FB2 - Customer Programmable Area Factory Programmed Area Reserved ...
Page 12
Mode Notes RST# Read Array Output Disable V IH Standby V IH Reset Read Identifier Codes/OTP V Read Query 6,7 IH Write 4,5 NOTES: 1. See DC Characteristics ...
Page 13
... OTP block (See Table 3 and Table 4). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked ...
Page 14
Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any valid ...
Page 15
State WP#/ACC [000] 0 (3) 0 [001] [011] 0 [100] 1 (3) 1 [101] (4) 1 [110] [111] 1 NOTES =1: a block is locked =1: a block is locked-down Erase ...
Page 16
Table 9. Block Locking State Transitions upon WP#/ACC Transition Previous State State - [000] - [001] (2) [011] [110] (2) Other than [110] - [100] - [101] - [110] - [111] NOTES: 1. "WP#/ACC=0→1" means that WP#/ACC is driven ...
Page 17
WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 ...
Page 18
SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ...
Page 19
Table 12. Partition Configuration Register Definition PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are ...
Page 20
Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...-40°C to +85°C Storage Temperature During under Bias............................... -40°C to +85°C During non Bias................................ -65°C to +125°C Voltage On Any Pin (except V and WP#/ACC)... ...
Page 21
Capacitance (T =+25°C, f=1MHz) A Parameter Symbol Input Capacitance WP#/ACC Input Capacitance Output Capacitance C NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CC INPUT 0.0 AC test inputs are driven at V ...
Page 22
DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Power-Down Current CCD CC Average V Read ...
Page 23
Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH WP#/ACC during Block Erase, Full V Chip Erase, (Page Buffer) Program or ACCH OTP Program Operations V ...
Page 24
AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High ...
Page 25
(A) 20 EHEL V IH CE# ( AVEL t AVGL t GHGL V IH OE# ( (W) WE High (D/Q) ...
Page 26
(A) 20 (A) 2 CE# ( OE# ( WE# ( High (D/Q) 15-0 ...
Page 27
(A) 20 AVQV V IH VALID A (A) 2-0 ADDRESS CE# ( ELQV V IH OE# ( WE# ( ...
Page 28
AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t ...
Page 29
NOTE 1 NOTE VALID A (A) 20-0 ADDRESS (E) CE ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# (W) V ...
Page 30
Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND ...
Page 31
Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / ...
Page 32
Related Document Information Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF32FB2 (1) Document Name LH28F320BF series Appendix 29 Rev. 2.44 ...
Page 33
...
Page 34
...
Page 35
...
Page 36
...
Page 37
...
Page 38
...
Page 39
...
Page 40
...
Page 41
...
Page 42
...
Page 43
... LH28F320BFXX-XXXXXX Flash MEMORY ERRATA 1. AC Characteristics PROBLEM The table below summarizes the AC characteristics. AC Characteristics - Write Operations Page Symbol t 25 AVAV WLWH ELEH WHWL EHEL WORKAROUND System designers should consider these specifications. STATUS This is intended to be fixed in future devices. V =2.7V-3.6V CC Parameter ...
Page 44
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
Page 45
A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
Page 46
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
Page 47
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
Page 48
A-3 STATUS REGISTER READ OPERATIONS If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit SR.15 instead of SR.7 to determine when the erase or program ...
Page 49
... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...