LH28F320BFHE-PTTL60 Sharp Electronics, LH28F320BFHE-PTTL60 Datasheet - Page 17

• Manufacturer Part Number: LH28F320BFHE-PTTL60
• Manufacturer: Sharp Electronics

Specifications of LH28F320BFHE-PTTL60

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 60ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 11.7 to 12.3V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

sharp
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.15 - SR.8 = RESERVED FOR FUTURE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
SR.4 = (PAGE BUFFER) PROGRAM AND
SR.3 = WP#/ACC STATUS (WPACCS)
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
1 = V
0 = WP#/ACC OK
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
1 = Erase or Program Attempted on a
0 = Unlocked
15
R
7
Operation Abort
Locked Block, Operation Abort
STATUS (BEFCES)
STATUS (PBPSS)
OTP PROGRAM STATUS (PBPOPS)
CC
+0.4V < WP#/ACC < 11.7V Detect,
BESS
14
R
6
BEFCES
13
R
5
Table 10. Status Register Definition
PBPOPS
12
R
4
LHF32FB2
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to 2,
3 or 4 partitions configuration.
Check SR.7 or RY/BY# to determine block erase, full chip
erase, (page buffer) program or OTP program completion.
SR.6 - SR.1 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit, set partition configuration register
attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of WP#/ACC
level. The WSM interrogates and indicates the WP#/ACC
level only after Block Erase, Full Chip Erase, (Page Buffer)
Program or OTP Program command sequences. SR.3 is not
guaranteed to report accurate feedback when WP#/
ACC≠V
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
WPACCS
11
R
3
ACCH
.
PBPSS
10
R
2
NOTES:
DPS
R
9
1
Rev. 2.44
R
R
8
0
14