TE28F400CVT80 Intel, TE28F400CVT80 Datasheet - Page 13

• Manufacturer Part Number: TE28F400CVT80
• Manufacturer: Intel

Specifications of TE28F400CVT80

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2.0
2.1
This product family features an asymmetrically-
blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 times for
commercial temperature or up to 10,000 times for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolatile storage. The combination
of block sizes in the boot block architecture allow
the integration of several memories into a single
chip. For the address locations of the blocks, see
the memory maps in Figures 4 and 5.
2.1.1
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address map
to accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combination of the V
WP# pins, as is detailed in Section 3.4.
SEE NEW DESIGN RECOMMENDATIONS
PRODUCT DESCRIPTION
Memory Blocking Organization
ONE 16-KB BOOT BLOCK
PP
, RP#, and
4-MBIT SmartVoltage BOOT BLOCK FAMILY
2.1.2
The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the byte-
rewrite functionality of EEPROMs can be emulated.
These techniques are detailed in Intel’s application
note, AP-604 Using Intel’s Boot Block Flash
Memory Parameter Blocks to Replace EEPROM .
Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.
2.1.3
After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 4-Mbit
device contains one 96-Kbyte (98,304 byte) block
and three 128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more information.
TWO 8-KB PARAMETER BLOCKS
ONE 96-KB + THREE 128-KB
MAIN BLOCKS
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