TE28F400CVT80 Intel, TE28F400CVT80 Datasheet - Page 29

• Manufacturer Part Number: TE28F400CVT80
• Manufacturer: Intel

Specifications of TE28F400CVT80

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4.2.1
When applying V
may be required before initiating device operation,
depending on the V
slower than 1V/100 µs (0.01 V/µs) then no delay is
NOTES:
1.
2.
3.
4.3
(T
NOTES:
1. Sampled, not 100% tested.
2. For the 28F004B, address pin A
> 1V/100 s
C
C
V
Symbol
A
IN
OUT
1V/100 s
CC
SEE NEW DESIGN RECOMMENDATIONS
= 25 °C, f = 1 MHz)
These requirements must be strictly followed to guarantee all other read and write specifications.
To switch between 3.3 V and 5 V operation, the system should first transition V
and then to the new voltage. Any time the V
pending or in progress.
These guidelines must be followed for any V
Ramp Rate
Capacitance
APPLYING V CC VOLTAGES
Input Capacitance
Output Capacitance
Parameter
CC
No delay required.
A delay time of 2 s is required before any device operation is initiated, including read
operations, command writes, program operations, and erase operations. This delay is
measured beginning from the time V
and 4.5 V for 5 V operation).
voltage to the device, a delay
CC
ramp rate. If V
10
follows the C
Note
1, 2
2
CC
CC
CC
OUT
supply drops below V
transition from GND.
ramps
capacitance numbers.
Typ
10
6
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Required Timing
CC
required. If V
V/µs), then a delay of 2 µs is required before
initiating
recommended during power-up to protect against
spurious write signals when V
and V
reaches V
CCMIN
CCMIN
, the chip may be reset, aborting any operations
device
Max
.
12
8
CCMIN
CC
CC
ramps faster than 1V/100 µs (0.01
from the existing voltage range to GND,
(3.0 V for 3.3
operation.
Unit
pF
pF
CC
RP#
V
V
IN
OUT
0.3 V operation;
is between V
Conditions
= 0 V
= 0 V
=
GND
LKO
29
is