MT4LC4M16F5TG-5 Micron Technology Inc, MT4LC4M16F5TG-5 Datasheet
MT4LC4M16F5TG-5
Specifications of MT4LC4M16F5TG-5
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MT4LC4M16F5TG-5 Summary of contents
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... FAST PAGE MODE (FPM) access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms OPTIONS • Plastic Package 50-pin TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rate Standard Refresh Part Number Example MT4LC4M16F5TG-5 KEY TIMING PARAMETERS SPEED RC RAC PC -5 90ns 50ns ...
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... FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an ...
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... DRAM REFRESH The supply voltage must be maintained at the speci- fied levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the DRAM array at least once every 64ms. The recom- mended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms ...
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... RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 WORD READ STORED OUTPUT OUTPUT STORED STORED DATA DATA DATA DATA DATA ADDRESS High-Z Figure 2 WORD and BYTE READ Example 4 4 MEG x 16 ...
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... REFRESH CURRENT: CBR Average power supply current t (RAS#, CAS#, address cycling Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
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... Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 = +3.3V ±0.3V SYMBOL MIN ...
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... Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 = +3.3V ±0.3V SYMBOL MIN ...
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... OFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/ 18. = +3.3V restrictive operating parameters. CC EARLY WRITE cycles. If cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle ...
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... Last rising CASx# edge to first falling CASx# edge. 32. First DQs controlled by the first CASx LOW. 33. Last DQs controlled by the last CASx HIGH. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 34. Each CASx# must meet minimum pulse width. 35. Last CASx LOW. 36. All DQs controlled, regardless CASL# and CASH#. 37. V ...
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... CAH 8 t CAS 13 10,000 t CLCH 5 t CLZ 3 t CRP 5 t CSH Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 READ CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH COLUMN t RCS RAC t CAC t CLZ OPEN -6 MAX UNITS SYMBOL t 30 ...
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... CAS 13 10,000 t CLCH 5 t CRP 5 t CSH 50 t CWL RAD 13 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 EARLY WRITE CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH COLUMN t CWL t RWL t WCR t WCS t WCH VALID DATA -6 MIN ...
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... CLCH 5 t CLZ 3 t CRP 5 t CSH 50 t CWD 36 t CWL Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 READ-WRITE CYCLE t RWC t RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH COLUMN t RWD t RCS t CWD t AWD RAC t CAC t CLZ OPEN t OE ...
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... CAH 8 t CAS 13 10,000 t CLCH 5 t CLZ CPA 30 t CRP 5 t CSH Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 FAST-PAGE-MODE READ CYCLE t RASP RCD t CAS ASC t CAH t ASC COLUMN COLUMN t RCS t RCH RAC t CAC t OFF t CLZ t CLZ VALID DATA MIN ...
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... ASR 0 t CAH 8 t CAS 13 10,000 t CLCH CRP 5 t CSH 50 t CWL Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 t RASP RCD t CAS ASC t CAH t ASC COLUMN COLUMN t CWL t WCH t WCS WCR VALID DATA VALID DATA -6 MIN MAX UNITS SYMBOL ...
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... CPA 30 t CRP 5 t CSH 50 t CWD 36 t CWL NOTE for LATE WRITE only. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 t RASP t CSH NOTE 1 t RCD t CAS ASC t CAH t ASC COLUMN COLUMN t RWD t RCS t CWL AWD t CWD CPA CAC t CAC ...
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... CRP 5 t CSH 50 t CWL NOTE not drive input data prior to output data going High-Z. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 (Pseudo READ-MODIFY-WRITE) t RASP t CSH t RCD t CAS RAD t RAH t ASC t CAH COLUMN t RCS t CAC t CLZ t OFF VALID OPEN DATA ...
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... CRP 5 t CSR 5 t RAH 8 NOTE: 1. End of first CBR REFRESH cycle. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) t RAS t RAH ROW OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) t RAS ...
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... CHR 15 t CLZ 3 t CRP NOTE HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW RAS RCD t RSH RAD t ASC t CAH COLUMN ...
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... Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 50-PIN PLASTIC TSOP (400 mil) .88 TYP 11 ...