MT4LC4M16F5TG-5 Micron Technology Inc, MT4LC4M16F5TG-5 Datasheet - Page 2

• Manufacturer Part Number: MT4LC4M16F5TG-5
• Manufacturer: Micron Technology Inc
• Type: FPMr

Specifications of MT4LC4M16F5TG-5

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 12b
• Access Time (max): 25ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 105mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

FAST PAGE MODE ACCESS
as mentioned in the General Description. Use of both
CAS# signals results in a word access via the 16 I/O pins
(DQ0-DQ15). Use of only one of the two results in a
BYTE access cycle. CASL# transitioning LOW selects an
access cycle for the lower byte (DQ0-DQ7), and CASH#
transitioning LOW selects an access cycle for the upper
byte (DQ8-DQ15). General byte and word access timing
is shown in Figures 1 and 2.
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For
example, an EARLY WRITE on one byte and a LATE
WRITE on the other byte are not allowed during the
same cycle. However, an EARLY WRITE on one byte and
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
WE#
RAS#
Each location in the DRAM is uniquely addressable,
Additionally, both bytes must always be of the same
A11
A0-
CASH#
CASL#
10
12
NO. 2 CLOCK
GENERATOR
NO. 1 CLOCK
GENERATOR
CONTROLLER
BUFFERS (12)
BUFFER(10)
COLUMN-
COUNTER
ADDRESS
ADDRESS
REFRESH
REFRESH
ROW-
12
CAS#
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M16F5 (12 row addresses)
12
10
4,096
2
a LATE WRITE on the other byte, after a CAS# precharge
has been satisfied, are permissible.
WRITE operation; otherwise a READ operation will be
performed. The OE# signal must be activated to enable
the DQ output drivers for a read access and can be
deactivated to disable output data if necessary.
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the FAST-PAGE-MODE
operation.
The WE# signal must be activated to execute a
FAST-PAGE-MODE operations are always initiated
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DATA-IN BUFFER
4,096 x 16
DATA-OUT
DECODER
COLUMN
4,096 x 1,024 x 16
BUFFER
SENSE AMPLIFIERS
1,024
I/O GATING
MEMORY
1,024 x 16
ARRAY
16
4 MEG x 16
FPM DRAM
16
16
16
©2000, Micron Technology, Inc.
OBSOLETE
V
V
DD
SS
DQ0-
DQ15
OE#