MT4LC4M16F5TG-5 Micron Technology Inc, MT4LC4M16F5TG-5 Datasheet - Page 8

• Manufacturer Part Number: MT4LC4M16F5TG-5
• Manufacturer: Micron Technology Inc
• Type: FPMr

Specifications of MT4LC4M16F5TG-5

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 12b
• Access Time (max): 25ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 105mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10. If CAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL
13. If CAS# is LOW at the falling edge of RAS#,
14. The
15. The
16. Either
17.
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
MHz.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
the last valid READ cycle.
gates, 100pF and V
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
and
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
t
cycle.
t
achieves the open circuit condition and is not
referenced to V
RCD (MAX) was specified as a reference point
RAD (MAX) was specified as a reference point
AA,
OFF (MAX) defines the time at which the output
DD
IH
is dependent on output loading and cycle
(MIN) and V
t
t
t
t
RCD (MAX) limit is no longer specified.
CAC must always be met.
RAD (MAX) limit is no longer specified.
RAC, and
t
RCH or
t
t
RCD was greater than the specified
RAD was greater than the specified
IL
IH
IH
IL
and V
and V
, data output may contain data from
, data output is High-Z.
t
t
t
OH
CAC (
AA (
t
RRH must be satisfied for a READ
CAC must always be met.
IL
or V
(MAX) are reference levels for
IH
IL
OL
t
).
RAC and
(or between V
t
= 0.8V and V
RAC [MIN] no longer
OL
.
t
T = 5ns.
SS
CC
.
t
IH
t
CAC no longer
t
RCD limit,
RAD (MAX) limit,
= +3.3V; f = 1
and V
OH
IL
and V
= 2V.
IL
(or
t
t
IH
t
AA
REF
CP.
t
t
) in a
RCD
RAD
8
18.
19. These parameters are referenced to CAS# leading
20. If OE# is tied permanently LOW, LATE WRITE, or
21. A HIDDEN REFRESH may also be performed after
22. RAS#-ONLY REFRESH requires that all 4,096 rows
23. The DQs go High-Z during READ cycles once
24. LATE WRITE and READ-MODIFY-WRITE cycles
25. Column address changed once each cycle.
26. The first CASx# edge to transition LOW.
27. The last CASx# edge to transition HIGH.
28. Output parameter (DQx) is referenced to
29. Last falling CASx# edge to first rising CASx#
t
restrictive operating parameters.
EARLY WRITE cycles. If
cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout
the entire cycle.
READ-MODIFY-WRITE cycles. Meeting these
limits allows for reading and disabling output
data and then applying input data. The values
shown were calculated for reference allowing
10ns for the external latching of read data and
application of write data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.
t
LATE WRITE cycle.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
READ-MODIFY-WRITE operations are not
possible.
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
be refreshed at least once every 64ms. CBR
REFRESH requires that at least 4,096 cycles be
completed every 64ms.
or
DQs will go High-Z regardless of the state of OE#.
If CAS# stays LOW while OE# is brought HIGH,
the DQs will go High-Z. If OE# is brought back
LOW (CAS# still LOW), the DQs will provide the
previously read data.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. If OE# is taken back LOW while CAS#
remains LOW, the DQs will remain open.
corresponding CAS# input; DQ0-DQ7 by CASL#
and DQ8-DQ15 by CASH#.
edge.
WCS,
RWD,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
OFF occur. If CAS# goes HIGH before OE#, the
t
t
RWD,
CWD, and
t
AWD, and
t
t
OD and
RWD,
t
AWD are not applicable in a
t
t
AWD and
WCS >
t
OEH met (OE# HIGH
t
CWD are not
4 MEG x 16
FPM DRAM
t
t
WCS (MIN), the
WCS applies to
©2000, Micron Technology, Inc.
t
CWD define
OBSOLETE
t
WCS,
t
OD