AM29F016B-90EC AMD (ADVANCED MICRO DEVICES), AM29F016B-90EC Datasheet - Page 8

• Manufacturer Part Number: AM29F016B-90EC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F016B-90EC

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 40mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend:
L = Logic Low = V
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.
8
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
(See Note)
IH
.
Operation
IL
, H = Logic High = V
CC1
in the DC Characteristics
Table 1. Am29F016B Device Bus Operations
IL
. CE# is the power
IH
, V
V
CC
ID
CE#
= 12.0
± 0.5 V
H
X
X
L
L
L
0.5 V, X = Don’t Care, D
Am29F016B
OE#
H
H
X
X
X
X
L
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
WE#
CC2
H
X
X
H
X
X
L
in the DC Characteristics table represents the ac-
IL
V
, and OE# to V
IN
RESET#
CC
= Data In, D
V
± 0.5 V
H
H
H
H
L
ID
OUT
IH
.
A0–A20
= Data Out, A
A
A
A
X
X
X
X
IN
IN
IN
IN
DQ0–DQ7
= Address In
High-Z
High-Z
High-Z
High-Z
D
D
D
OUT
IN
IN