5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 51

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
LD7 – LD0
LA7 - LA0
IACKOUT
IRQ7 - IRQ1
DS
DSACK1,
DSACK0
LBERR
RESET
CS
PAS
Symbol
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The VMEbus daisy-chained interrupt-acknowledge-out signal is an output.
The VMEbus interrupt request signals are both inputs and open collector outputs.
The local data 7 - 0 signals are both inputs and three-state outputs. These signals are typically
connected to the local processor data lines D[7:0] through an isolation buffer. Device register accesses
are also made through these data signals.
The local address 7 - 0 signals are both inputs and three-state outputs. These signals are typically
connected to the local processor address lines. VIC068A registers are also addressed through these
signals. When acting as the local bus master, the device drives these lines with the LAEN signal to
supply the local address.
The device chip select signal is an input. This signal should be asserted whenever access to the device
internal registers is required.
The physical/processor address strobe signal is both an input and a rescinding output. This signal is
used to qualify an incoming address when performing VMEbus master operations or register operations.
refresh, slave block transfers, and block transfers with local DMA. When acting as an output, the
minimum assertion and negation timing for this signal is directed by the Local Bus Timing Register.
The local data strobe signal is both an input and a rescinding output. This signal is used to qualify
incoming data when performing VMEbus master operations or register operations. This signal is driven
when becoming the local bus master and performing slave transfers, DRAM refresh, slave block
transfers, and block transfers with local DMA. When acting as an output, the minimum assertion and
negation timing for this signal is directed by the Local Bus Timing Register.
The local data-size-acknowledge signals are both inputs and rescinding outputs. One or both DSACK0
of these signals should be asserted to the device whenever the device is local bus master to
acknowledge the successful completion of each cycle of a slave transfer, slave block transfer, or block
transfers with local DMA. The device asserts one or both of these signals to acknowledge the
successful completion of a VMEbus master operation (after receiving the VMEbus DTACK signal. The
following should be noted about the DSACK1/0 signals:
* The device only asserts a 16 bit
to a D16 VMEbus resource is complete.
* The device treats the assertion of any
* The device does not directly support 16 or 8-bit local port sizes.
* The device always asserts both
cycles.
The local bus-error signal is both an input and a rescinding output. This signal should be asserted to
the device whenever the device is local bus master to acknowledge the unsuccessful completion of a
cycle of a slave transfer, slave block transfer, and block transfers with local DMA in which case the
device asserts the VMEbus BERR signal. The device asserts this signal to acknowedge the
unsuccessful completion of a VMEbus master operation (after receiving the VME-bus BERR signal).
The local reset indication signal is an open collector output. This signal is asserted whenever the device
is in a reset condition. An internal global, or system reset causes the device to assert RESET for a
minimum of 200 ms. If the reset condition continues for longer than 200 ms, RESET begins additional
200 ms timeouts until all reset conditions are cleared.
This signal is driven when becoming the local bus master and performing slave transfers, DRAM
STANDARD
TABLE III. Pin description - Continued.
DSACK for register accesses, as well as for interrupt acknowledge
DSACK code when the WORD signal is asserted indicating access
DSACK signal as a 32-bit acknowledge for slave accesses.
s
i
Name and function
i
SIZE
A
REVISION LEVEL
B
SHEET
5962-92010
51