5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 55

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
CLK64M
LAEN
LADO
LADI
BLT
DEDLK
ABEN
Symbol
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The block transfer with local DMA indication signal is both an input and an open-collector output. This
signal is used to indicate that a block transfer with local DMA is in progress. This signal remains
asserted for the entire block transfer including interleave periods with the exception of local page
boundary crossings. BLT toggles during local boundary crossings to increment the external LA(+:8)
counters. The BLT signal is asserted simultaneously with the MWB signal and BTCR signal is
asserted simultaneously with the MWB signal and BTCR[7] is set, a module-based DMA transfer is
performed.
The dead-lock indication signal is an output. This signal is used to indicate a dead-lock condition has
occured. This signal should be used by local logic to remove its request for the VMEbus. DEDLK
remains asserted until the slave transaction is complete.
interleave period of a block transfer with local DMA, without the dual path feature enabled. In this case,
asserted after the VMEbus has been re-obtained, the device will assert DEDLK for the duration of the
burst.
The device master clock is an input. This 64-MHz clock input is used to clock internal arbitration,
timing, and delay functions within the device.
The VMEbus address bus enable signal is an output. This signal is used to enable the external VMEbus
address drivers for VMEbus master operations. It is typically connected to the QEAB input of a '543
address transceiver.
The local address enable signal is an input. This signal is used to enable the external local address
drivers for slave accesses. It is typically connected to the OEBA input of a '543 address transceivers
through an inverter. This signal is an active HIGH signal.
The latch address out signal is an output. This signal is used to latch the outgoing VMEbus address for
VMEbus master operations. When this signal is asserted (HIGH), it is assumed that the latches are in a
latched state. When negated, the latches should be in a fall-through state. This allows direct
connection to the '543 address driver LEAB input. LADO is very important for proper operation of
master write posting and block transfers with interleave periods. For these operations, device may use
LADO in combination with LADI and ABEN to temporarily store the contents of a VMEbus address
during intervening slave accesses.
The latch address in signal is an input. This signal is used to latch the incoming VMEbus address for
slave accesses. When this signal is asserted (HIGH), it is assumed that the latches should be in a
latched state. When negated, the latches should be in a fall-through state. This allows direct
connection to the '543 address driver LEAB input. LADI is used in conjunction with LADO to temporarily
store outgoing VMEbus master transaction addresses during intervening slave accesses.
DEDLK is also asserted to indicate that a VMEbus master cycle is being attempted during the
DEDLK is asserted while MWB signal is asserted. If, during the interleave period, the MWB signal is
STANDARD
TABLE III. Pin description - Continued.
Name and function
SIZE
A
REVISION LEVEL
B
SHEET
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