5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 56

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
LEDO
LEDI
DDIR
LWDENIN
UWDENIN
ISOBE
RMC
DENO
SWDEN
Symbol
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The lower word data enable in signal is an output. This signal enables data onto the lower word of the
local data bus LD[15:8] for master read and slave write cycles. This signal is typically connected to the
OEBA input of the '543 lower data latch.
The upper word data enable in signal is an output. This signal enables data onto the upper word of the
local data bus LD[31:16] for master read and slave write cycles. This signal is typically connected to the
OEBA input of the upper '543 data latches.
The latch data out signal is an output. This signal latches the outgoing VMEbus data for master write
slave read cycles. When this signal is asserted (HIGH), it is assumed that the latches are in a latched
state. When negated, the latches should be in a fall-through state. This allows direct connection to the
'543 address driver LEAB input. This signal is used in conjunction with LEDI to temporarily store
outgoing master write post data (data switch-back).
The latch data in signal is an output. This signal latches the incoming VMEbus data for master read
slave write cycles. When this signal is asserted (HIGH), it is assumed that the latches are in a latched
state. When negated, the latches should be in a fall-through state. This allows direct connection to the
'543 address driver LEBA input. This signal is used in conjunction with LEDO to temporarily store
outgoing master write post data.
The isolation buffer enable signal. This signal, along with the SWDEN signal, provides byte lane
switching. This signal is typically connected to the EN input of the '245 isolation buffer.
The swap data enable signal is an output. This signal, along with the ISOBE signal, provides byte lane
switching. It provides for swapping LD[31:16] to LD[15:0]. This signal is typically connected to the EN
input of the '245 swap buffer.
The data direction signal is an output. This signal provides the data direction (i.e., read/write)
information to the isolation and swap buffers. When asserted, buffers should be configured in the Iocal-
to-VME-bus (A-to-B) direction. This signal is typically connected to the DIR input of the ‘245 isolation
swap buffers.
This is the read-modify-write control signal. This signal may be used to control indivisible cycles on the
VMEbus. Its operation is controlled with the interface configuration register, bits 5-7
The Data Enable Out signal is an output. This signal enables data onto the VMEbus data bus for
Master Write and Slave Read cycles. The signal is typically connected to the OAEB input of the ‘543
data latches.
STANDARD
TABLE III. Pin description - Continued.
Name and function
SIZE
A
REVISION LEVEL
B
SHEET
5962-92010
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