5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 53

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
ASIZ1,
ASIZ0
ICFSEL
MWB
FCIACK
LBR
LBG
SLSEL1 ,
SLSEL0
Symbol
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The local bus request signal is an output. This signal is asserted whenever the device desires
mastership of the local bus. This signal remains asserted for the entire bus tenure. Local bus
mastership is requested when each of the following operations is desired:
The interprocessor communication facility (ICF) select signal. This signal is used to indicate that the
ICF functions of the device have been selected. These include the ICF registers and the ICF switch
interrupts. This signal is qualified with AS and A16 AM codes (A16/Supervisory for global switches).
The local bus grant signal is an input. The signal should be asserted in response to the assertion of the
signal should remain asserted for the duration of LBR .
The module-wants-bus signal. This signal should be asserted by local resources to begin a VMEbus
transaction. When qualified by the PAS signal, the device asserts the VMEbus BRi signal. This signal
is usually asserted by Iocal-to-VMEbus address decoders.
The local interrupt acknowledge signal is an input. This signal should be asserted (qualified by PAS ) to
acknowledge all device-generated local interrupts.
The slave select signals. These signals indicate the device has been selected to perform a SLSEL0
VMEbus SLSEL0 slave operation. When qualified by AS and valid AM codes, the device requests the
local bus to perform the slave cycle. These signals are usually asserted by VMEbus-to- local address
decoders. The SLSEL1/0 signals may be used independently of each other to provide unique slave
characteristics as defined by the Slave Select Control registers.
The VMEbus address size signals are inputs. These signals should be driven to indicate the ASIZ0
VMEbus address size of master VMEbus transfers. The address size information is issued on the
VMEbus AM codes. The assertion of ASIZ0 indicates an A16 transaction. The assertion of ASIZ1
indicates an A32 transaction. Asserting neither indicates an A24 transaction. User-defined address
spaces may be accessed by asserting both ASIZ1/0 signals. In this case, the AM codes are issued
according to the programming of the Address Modifier Source Register.
The ASIZ1/0 signals are also used for cycle acknowledge signals for module-based DMA transfers.
During a module-based DMA transfer, the ASIZ0 signal is used as a data-transfer acknowledge signal
(analogous to DTACK ). The ASIZ1 signal is used as a bus-error signal (analogous to BERR ).
LBR signal. The device does not incorporate a local bus grant acknowledge protocol so the LBG
* Standard slave accesses
* Slave block transactions
* Block transfers with local DMA
* DRAM refresh
STANDARD
ASIZ1
0
0
1
1
TABLE III. Pin description - Continued.
ASIZ0
0
1
0
1
Address Size
User Defined
A32
A16
A24
Name and function
SIZE
A
REVISION LEVEL
B
SHEET
5962-92010
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