5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 54

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
LIRQ7 -
LIRQ1
IPL2 , IPL1 ,
IPL0
LIACKO
IRESET
WORD
SCON
Symbol
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The VMEbus data-width control signal is an input. This signal, when asserted indicates the requested
VMEbus transaction should be treated as a D16 data path. When negated, the VMEbus data path is
assumed to be D32. This signal should be used to configure VMEbus data-width for master cycles only.
to configure the data-width for block transfers with local DMA. When this signal is asserted during the
block transfer initiation cycle, the block transfer is assumed to be a D16 block transfer. This signal may
be changed dynamically for individual transfers, or strapped LOW at power-up for permanent D16
operation. If WORD is strapped LOW at power-up, the device is configured as a D16 slave
independent of the slave configuration in the Slave Select Control Registers. WORD should not be
used to indicate data size (i.e., byte, word, or long-word) only local data port size (i.e., D16 or D32).
The local interrupt request signals are inputs with LIRQ2 also available as an output. These LIRQi
signals serve as local interrupt request signals for the device. If enabled to handle the particular local
interrupt, the device in turn issues a processor interrupt with the IPLi signals at the assertion of a
Registers. LIRQ2 may also be configured to issue periodic interrupts at user defined intervals.
The local priority encoded interrupt request signals are outputs with IPL0 also available as an input.
These signals are asserted to interrupt the local processor. All local device interrupts are issued with
these signals. These signals are meant to emulate the Motorola 68K interrupt algorithms. The
assertion of one or more of these signals indicate a single interrupt with a priority given by the negative-
logic value of the IPLi signals. Level 7 is the highest priority. These signals are open-collector to allow
the wire-O Ring of multiple interrupt sources.
During the assertion of IRESET , IPL0 becomes an input . If I IPL0 is asserted at this time, a global
reset is performed.
The autovectoring indication signal is an input. This signal is asserted when the device is configured to
allow the interrupting device to place its status/ID vector on the local data bus in response to a device-
handled local interrupt acknowledge. This signal may be used to signal a autovectored interrupt
acknowledge cycle for 68020/30/40 processors. This signal may be connected directly to the AVEC
signal for these processors.
The Internal reset signal is an input. This signal is used to issue both internal and global resets to the
device. If asserted with IPL0 , a global reset is performed. If asserted without IPL0 , an internal reset is
performed. All internal state machines and selected register bits are rese during the assertion of
system controller, SYSRESET is also asserted during the assertion of IRESET .
power-up resets.
The system controller enabling signal is an input. This signal is used to configure the device as
VMEbus system controller. This signal must be strapped Iow at power-up and remain LOW for device
to reliably assume the role of VMEbus system controller.
LIRQi . Extensive configuration of local interrupts is allowed through the Local Interrupt Configuration
IRESET . HALT and RESET are both asserted during the assertion of IRESET . If configured as
IRESET contains internal hysteresis to allow the connection of this signal to an external RC network for
Data-width for slave cycles is configured in the Slave Select Control Registers. This signal is also used
STANDARD
TABLE III. Pin description - Continued.
Name and function
SIZE
A
REVISION LEVEL
B
SHEET
5962-92010
54