CY7C1381C-100AI Cypress Semiconductor Corp, CY7C1381C-100AI Datasheet - Page 14

• Manufacturer Part Number: CY7C1381C-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381C-100AI

• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05238 Rev. *B
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Snooze Mode, Pow-
er-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Notes:
9
DDZZ
ZZS
ZZREC
ZZI
RZZI
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE
Parameter
after the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Cycle Description
[ 3, 4, 5, 6, 7]
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
1
, CE
2
, CE
ADDRESS
External
External
External
External
External
Used
None
None
None
None
None
None
Next
Next
3
[2]
Description
, ADSP, and ADSC must
ZZREC
CE
after the ZZ input
H
X
X
X
X
L
L
L
L
L
L
L
L
1
CE
H
H
H
H
H
X
X
X
X
X
X
L
L
2
CE
X
X
H
X
X
X
X
X
L
L
L
L
L
3
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
ZZ > V
ZZ < 0.2V
ZZ > V
This parameter is sampled
This parameter is sampled
.
ADSP
Test Conditions
DD
DD
X
H
H
X
H
H
H
H
H
L
L
L
L
– 0.2V
– 0.2V
ADSC
X
X
X
X
X
H
H
L
L
L
L
L
L
ADV WRITE
X
X
X
X
X
X
X
X
X
X
X
L
L
X
. Writes may occur only on subsequent clocks
2t
X
X
H
H
H
H
X
X
X
X
X
X
L
Min.
CYC
0
OE
X
X
X
X
H
X
H
H
X
X
L
L
L
CY7C1381C
CY7C1383C
2t
2t
Max.
60
CYC
CYC
CLK
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
X
Page 14 of 36
Tri-State
Unit
DQ
mA
ns
ns
ns
ns
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