CY7C1381C-100AI Cypress Semiconductor Corp, CY7C1381C-100AI Datasheet - Page 6

• Manufacturer Part Number: CY7C1381C-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381C-100AI

• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05238 Rev. *B
CY7C1381C–Pin Definitions
A
BW
BW
GW
CLK
CE
CE
CE
OE
ADV
ADSP
0
, A
Name
1
2
3
A,
C,
[2]
1
BW
BW
, A
B
D
37,36,32,33,34,
35,42,43,44,45,
46,47,48,49,50,
81,82,99,100
93,94,95,96
Enable)
(3-Chip
TQFP
88
89
98
97
92
86
83
84
P4,N4,A2,B2,C2
T5,A6,B6,C6,R6
,R2,A3,B3,C3,T
3,T4,A5,B5,C5,
L5,G5,G3,L3
Enable)
(1-Chip
BGA
G4
H4
K4
E4
F4
A4
-
-
R6,P6,A2,A10,
B2,B10,N6,P3,
P11,R3,R4,R8,
P4,P8,P9,P10,
B5,A5,A4,B4
R9,R10,R11
Enable)
(3-Chip
fBGA
B7
B6
A3
B3
A6
B8
A9
B9
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
I/O
Address Inputs used to select one of the
512K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is
active LOW, and CE
sampled active. A
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of
CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled
on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device. ADSP is ignored
if CE
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled
on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.
Output Enable, asynchronous input,
active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.
Advance Input signal, sampled on the
rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE
[A:D]
1
is HIGH.
and BWE).
[1:0]
are also loaded into the burst
Description
1
[1:0]
is deasserted HIGH
2
1
1
1
, CE
and CE
and CE
and CE
feed the 2-bit counter.
CY7C1381C
CY7C1383C
2
, and CE
2
3
3
[2]
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