CY7C1381C-100AI Cypress Semiconductor Corp, CY7C1381C-100AI Datasheet - Page 31

• Manufacturer Part Number: CY7C1381C-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381C-100AI

• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05238 Rev. *B
Timing Diagrams
Read/Write Cycle Timing
Note:
21. On this diagram, when CE is LOW: CE
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC .
24. GW is HIGH.
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Data Out (Q)
Data In (D)
BWE, BW
ADDRESS
ADSP
ADSC
ADV
CLK
OE
CE
X
A1
High-Z
t ADS
Back-to-Back READs
t CES
t AS
(continued)
Q(A1)
A2
t ADH
[21, 23, 24]
t CEH
t
t AH
CH
t CYC
t
CL
1
Q(A2)
is LOW, CE
t
OEHZ
A3
2
is HIGH and CE
Single WRITE
t
t DS
WES
D(A3)
t DH
t
WEH
3
is LOW. When CE is HIGH: CE
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
X
LOW.
UNDEFINED
Q(A4+1)
BURST READ
1
is HIGH or CE
Q(A4+2)
2
is LOW or CE
Q(A4+3)
CY7C1381C
CY7C1383C
3
D(A5)
is HIGH.
Back-to-Back
A5
Page 31 of 36
WRITEs
D(A6)
A6
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