XPC850ZT50B Freescale Semiconductor, XPC850ZT50B Datasheet - Page 4
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XPC850ZT50B
Manufacturer Part Number
XPC850ZT50B
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.XPC850ZT50B.pdf
(76 pages)
Specifications of XPC850ZT50B
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 95C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
XPC850ZT50B
Manufacturer:
SHARP
Quantity:
686
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Manufacturer:
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Quantity:
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Part Number:
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Part Number:
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Manufacturer:
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Quantity:
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4
• Advanced on-chip emulation debug mode
• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
• Completely static design (0–80 MHz operation)
• System integration unit (SIU)
• Memory controller (eight banks)
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
— Memory management units (MMUs) with 8-entry translation lookaside buffers
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified
— Twenty-six external address lines
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC
— Reset controller
— IEEE 1149.1 test access port (JTAG)
— Glueless interface to DRAM single in-line memory modules (SIMMs),
— Memory controller programmable to support most size and speed memory
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
(TLBs) and fully-associative instruction and data TLBs
Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups
little-endian memory systems
architecture
synchronous DRAM (SDRAM), static random-access memory (SRAM),
electrically programmable read-only memory (EPROM), flash EPROM, etc.
interfaces
Freescale Semiconductor, Inc.
MPC850 (Rev. A/B/C) Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA