XPC850ZT50B Freescale Semiconductor, XPC850ZT50B Datasheet - Page 6
![](/photos/31/30/313042/406-256-bga_sml.jpg)
XPC850ZT50B
Manufacturer Part Number
XPC850ZT50B
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.XPC850ZT50B.pdf
(76 pages)
Specifications of XPC850ZT50B
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 95C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XPC850ZT50B
Manufacturer:
SHARP
Quantity:
686
Part Number:
XPC850ZT50B
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
XPC850ZT50B-0K24A
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
XPC850ZT50BU
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
6
• QUICC multichannel controller (QMC) microcode features
• One universal serial bus controller (USB)
• Two serial management controllers (SMCs)
• One serial peripheral interface (SPI)
• One I
• Time slot assigner
• Low-power support
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel
— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division-multiplexed (TDM) channel
— Supports master and slave modes
— Supports multimaster operation on the same bus
— Supports master and slave modes
— Supports multimaster environment
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate,
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
user-defined
2
C
®
(interprocessor-integrated circuit) port
®
Freescale Semiconductor, Inc.
MPC850 (Rev. A/B/C) Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA