PCF8576CH NXP Semiconductors, PCF8576CH Datasheet - Page 18

• Manufacturer Part Number: PCF8576CH
• Manufacturer: NXP Semiconductors

Specifications of PCF8576CH

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 20
• Number Of Segments: 160
• Package Type: LQFP
• Pin Count: 64
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 315KHz
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
PCF8576C_9
Product data sheet
7.10 Backplane outputs
7.11 Display RAM
7.7 Display register
7.8 Shift register
7.9 Segment outputs
The lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I
process a display data byte before the next one arrives, it holds the SCL line LOW until the
first display data byte is stored. This slows down the transmission rate of the I
no data loss occurs.
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
The shift register transfers display information from the display RAM to the display register
while previous data is displayed.
The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data residing in the display register. When less than
40 segment outputs are required, the unused segment outputs should be left open-circuit.
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit.
The display RAM is a static 40
bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off-state. There is a direct relationship between the RAM addresses and the
segment outputs, and between the individual bits of a RAM word and the backplane
outputs. The display RAM bit map
the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2
and BP3 respectively.
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In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
Rev. 09 — 9 July 2009
4-bit RAM which stores LCD data. A logic 1 in the RAM
Figure 12
Universal LCD driver for low multiplex rates
shows the rows 0 to 3 which correspond with
2
C-bus. When a device is unable to
PCF8576C
© NXP B.V. 2009. All rights reserved.
2
C-bus but
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