PCF8576CH NXP Semiconductors, PCF8576CH Datasheet - Page 21

• Manufacturer Part Number: PCF8576CH
• Manufacturer: NXP Semiconductors

Specifications of PCF8576CH

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 20
• Number Of Segments: 160
• Package Type: LQFP
• Pin Count: 64
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 315KHz
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
PCF8576C_9
Product data sheet
7.14.1 Output bank selector
7.12 Data pointer
7.13 Sub-address counter
7.14 Bank selector
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load data pointer command (see
stored starting at the display RAM address indicated by the data pointer (see
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD configuration.
The contents of the data pointer are incremented as follows:
If an I
Consequently, the data pointer must be rewritten prior to further RAM accesses.
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device select command (see
counter and the hardware subaddress do not match then data storage is blocked but the
data pointer will be incremented as if data storage had taken place. The subaddress
counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576C occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
The output bank selector (see
address for transfer to the display register. The actual bit selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
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In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit 1, bit 2 and then bit 3.
In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.
In 1:2 multiplex mode: bits 0 and 1 are selected.
In the static mode: bit 0 is selected.
2
C-bus data access terminates early, the state of the data pointer is unknown.
Rev. 09 — 9 July 2009
Table
15), selects one of the four bits per display RAM
Universal LCD driver for low multiplex rates
Table
14). If the contents of the subaddress
Table
13). After this, the data byte is
PCF8576C
© NXP B.V. 2009. All rights reserved.
Figure
21 of 56
13).