N28F001BXT150 Intel, N28F001BXT150 Datasheet
N28F001BXT150
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N28F001BXT150 Summary of contents
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... Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... Programming Equipment .................... 13 3.5.2 In-System Programming ..................... 13 3.6 Write .......................................................... 13 4.0 COMMAND DEFINITIONS............................ 13 4.1 Read Array Command ............................... 13 4.2 Intelligent Identifier Command for In-System Programming ............................................ 14 4.3 Read Status Register Command ............... 15 4.4 Clear Status Register Command ............... 15 4.5 Erase Setup/Erase Confirm Commands .... 15 4.6 Erase Suspend/Erase Resume Commands15 4 ...
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REVISION HISTORY Number -004 Removed Preliminary classification. Latched address A in Figure 5. 16 Updated Boot Block Program and Erase section: “If boot block program or erase is attempted while RP ‘1,’ reflective of the ...
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... The Intel ® 28F001BX Flash Boot Block memory augments the nonvolatility, in-system electrical erasure and reprogrammability of Intel’s flash memory by offering four separately erasable blocks and integrating a state machine to control erase and program functions. The specialized blocking architecture and automated programming ...
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Figure 1. 28F001BX Block Diagram 6 29040601 ...
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Table 1. Lead Descriptions Symbol Type A 0 –A 16 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle –DQ 7 INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during memory write OUTPUT cycles; ...
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Figure 3. PLCC Lead Congfiguration 28F001BX 29040604 9 ...
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... Write cycles also internally latch addresses and data needed for programming or erase operations. appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output program and erase status for verification. 29040606 pin enables successful altering memory ...
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... Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the status register. Programming is similarly controlled, after destination address and expected data are supplied. The program algorithm of past Intel Flash memories is now regulated by the state machine, including ...
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... Read The 28F001BX has three read modes. The memory can be read from any of its blocks, and information can be read from the intelligent identifier or the status register. V can be at either PPL The first task is to write the appropriate Read Mode ...
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... V to read the intelligent PP identifiers from the command register. 3.6 Write Writes to the command register allow read of device data and intelligent identifiers. They also control inspection and clearing of the status register. Additionally, when PPH register controls device erasure and programming. ...
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... IID = Data read from intelligent identifiers. 4. Following the Intelligent Identifier command, two read operations access manufacture and device codes. 5. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 14 4.2 Intelligent Identifier Command for In-System Programming ...
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Read Status Register Command The 28F001BX contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time ...
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At this point, a Read Array command can be written to the command register to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and ...
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... Block erasure or < a repeat of byte programming will initialize this data PPL to a known value. 7.0 ON-CHIP ERASE ALGORITHM As above, the quick-erase algorithm of prior Intel Flash memory devices internally, including all preconditioning of block data. WSM operation, erase success and V voltage presence are monitored and reported through the status register ...
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The entire sequence is performed with V PP Abort occurs when RP# transitions to V falls while erase is in progress. Block data PPL is partially erased by this operation, and a repeat of erase is ...
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Start Write 40H, Byte Address Write Byte Address/Data Read Status Register No SR Yes Full Status Check if Desired Byte Program Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register No No Suspend SR Erase? Yes Full Status Check if Desired Block Erase Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) No ...
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Start Write B0H Write 70H Read Status Register 0 SR SR.6 = Erase Resumed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Array Data Erase Resumed Figure 10. 28F001BX Erase ...
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... DESIGN CONSIDERATIONS Flash memories are often used in larger memory arrays. Intel provides three control inputs to accommodate multiple memory connections. Three- line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE#, while OE# should be connected to all memory devices and the system’ ...
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... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases usable battery life because the 28F001BX does not consume any power to retain code or data when the system is off ...
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ELECTRICAL SPECIFICATIONS 10.1 Absolute Maximum Ratings* Operating Temperature During Read................................. 0 ° °C During Erase/Program.................. 0 ° °C Operating Temperature During Read ........................... –40 °C to +85 °C During Erase/Program............ –40 °C to +85 ...
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... PPE Erase Suspend Current PPES Intelligent Identifier Current Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Intelligent Identifier Voltage ID 9 Notes Min Typ Max Unit Test Conditions 1 ±1.0 µ ±10 µ OUT 1.2 2.0 ...
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DC Characteristics (Continued) Symbol Parameter V V during Normal Operations PPL during Prog/Erase Operations PPH Erase/Write Lock Voltage LKO CC V RP#, OE# Unlock Voltage HH NOTES: 1. All currents are in ...
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... Intelligent Identifier Current Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage (TTL) OH1 V Output High Voltage (CMOS) OH2 V A Intelligent Identifier Voltage during Normal Operations PPL during Prog/Erase PPH PP Operations V V Erase/Write Lock Voltage LKO CC V ...
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Input 0.8 0.45 AC test inputs are driven for a Logic "1" and V OH TTL (2 and V (0 Output timing ends at V TTL IL TTL ...
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AC Characteristics—Read-Only Operations Version (2)a Symbol Parameter t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t CE# to Output Delay ELQV RP# High to Output Delay PHQV PWH ...
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Figure 14. AC Waveform for Read Operations 30 29040612 ...
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AC Characteristics—Write/Erase/Program Operations Versions Symbol Parameter t t Write Cycle Time AVAV RP# High Recovery to WE# Going Low PHWL CE# Setup to WE# Going Low ELWL WE# Pulse Width ...
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... Refer to Table 3 for valid D for byte programming or block erasure The on-chip WSM incorporates all program and erase system functions and overhead of standard Intel Flash memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing). 6. ...
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Figure 15. 28F001BX Typical Programming Capability Figure 16. 28F001BX Typical Programming Time 29040619 Figure 17. 28F001BX Typical Erase Capability 29040620 Figure 18. 28F001BX Typical Erase Time 28F001BX 29040621 29040622 33 ...
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Figure 19. AC Waveform for Write Operations 34 29040613 ...
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Figure 20. Alternate Boot Block Access Method Using OE# 28F001BX 29040615 35 ...
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AC Characteristics—CE#-Controlled Write Operations Versions V CC Symbol Parameter t t Write Cycle Time AVAV RP# High Recovery to CE# Going PHEL PS Low t t WE# Setup to CE# Going Low WLEL WS t ...
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NOTES: 1. Chip-enable controlled writes: write operations are driven by the valid combination of CE# and WE#. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should ...
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Figure 21. Alternate AC Waveform for Write Operations 38 29040616 ...
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... AP-623 Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...