AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 26

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

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Step 1 HOLD places the microprocessor in Snooping
Step 2 EADS and INV are asserted. If INV is 0, snoop-
Step 3 Two clock cycles after EADS is asserted, HITM
Step 4 In the next clock the core system logic deasserts
Step 5 The snooping cache starts its write-back of the
Step 6 The write-back access is finished when BLAST
Step 7 In the clock cycle after the final write-back ac-
HITM
CLK
ADS
BLAST
BRDY
HOLD
HLDA
mode. HLDA must be High for a minimum of
one clock cycle before EADS assertion. In the
fastest case, this means that HOLD asserts one
clock cycle before the HLDA response.
ing is caused by a read access. If INV is 1,
snooping is caused by a write access. EADS is
not sampled again until after the modified line
is written back to memory. It is detected again
as early as in Step 11.
becomes valid, and is 0 because the line is mod-
ified.
the HOLD signal in response to the HITM = 0.
The core system logic backs off the current bus
master at the same time so that the micropro-
cessor can access the bus. HOLD can be re-
asserted immediately after ADS is asserted for
burst cycles.
modified line by asserting ADS = 0, CACHE = 0,
and W/R = 1. The write access is a burst write.
The number of clock cycles between deassert-
ing HOLD to the snooping cache and first as-
serting ADS for the write-back cycles can vary.
In this example, it is one clock cycle, which is
the shortest possible time. Regardless of the
number of clock cycles, the start of the write-
back is seen by ADS going Low.
and BRDY both are 0.
cess, the processor drives HITM back to 1.
Figure 10. Valid HOLD Assertion During Write-Back
Enhanced Am486DX Microprocessor Family
Valid Hold Assertion
P R E L I M I N A R Y
Step 8 HOLD is sampled by the microprocessor.
Step 9 A minimum of 1 clock cycle after the completion
Step 10 The core system logic removes hold-off control
Step 11 The bus master restarts the aborted access.
The status of the addressed line is now either shared
(INV = 0) or is changed to invalid (INV = 1).
3.8.5.1
When designing a write-back cache system that uses
HOLD/HLDA as the bus arbitration method, the follow-
ing considerations must be observed to ensure proper
operation (see Figure 10).
Step 1 During a snoop to the on-chip cache that hits a
Step 2 After the write-back has commenced, the HOLD
of the pending access, HLDA transitions to 1,
acknowledging the HOLD request.
to the external bus master. This allows the ex-
ternal bus master to immediately retry the abort-
ed access. ADS is strobed Low, which
generates EADS Low in the same clock cycle.
EADS and INV are applied to the microproces-
sor as before. This starts another snoop cycle.
modified cache line, the HOLD signal cannot
be deasserted to the microprocessor until the
next clock cycle after HITM transitions active.
signal should be asserted no earlier than the
next clock cycle after ADS goes active, and no
later than in the final BRDY of the last write.
Asserting HOLD later than the final BRDY may
allow the microprocessor to permit a pending
access to begin.
HOLD/HLDA Write-Back Design
Considerations