GS8342T36AE-250 GSI TECHNOLOGY, GS8342T36AE-250 Datasheet
GS8342T36AE-250
Specifications of GS8342T36AE-250
Related parts for GS8342T36AE-250
GS8342T36AE-250 Summary of contents
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... B4 RAM is always one address pin less than the advertised index depth (e.g., the has a 2M addressable index). Parameter Synopsis -333 -300 -250 -200 3.0 ns 3.3 ns 4.0 ns 5.0 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 1/37 167 MHz–333 MHz 1 1.8 V and 1.5 V I/O Bottom View -167 6.0 ns 0.5 ns © 2006, GSI Technology DD ...
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... Expansion Addresses A10 72Mb A2 144Mb 2/ BW1 BW0 DQ17 DQ15 SS DDQ DDQ DDQ DDQ DDQ REF DQ13 DD DDQ DQ12 DD DDQ DDQ DQ11 DQ9 TMS © 2006, GSI Technology 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI ...
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... DDQ Bump BGA— Body—1 mm Bump Pitch Expansion Address A2 72Mb A7 144Mb B5 288Mb 3/ BW0 DQ7 DDQ DDQ DDQ DDQ DDQ REF DQ4 DD DDQ DDQ DDQ DQ1 TMS © 2006, GSI Technology 11 CQ DQ8 NC NC DQ6 DQ5 DQ3 DQ2 NC NC DQ0 TDI ...
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... V V DDQ DDQ DDQ DDQ DDQ Bump BGA— Body—1 mm Bump Pitch Expansion Address A2 72Mb A7 144Mb B5 288Mb 4/ DDQ DDQ DDQ DDQ DDQ REF DQ2 DD DDQ DDQ DDQ TMS © 2006, GSI Technology 11 CQ DQ4 NC NC DQ3 DQ1 NC NC DQ0 TDI ...
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... V V DDQ DDQ DDQ DDQ DDQ DDQ Bump BGA— Body—1 mm Bump Pitch Expansion Address A2 72Mb A7 144Mb B5 288Mb 5/ NW0 DDQ DDQ DDQ DDQ DDQ REF DQ1 DD DDQ DDQ DDQ TMS © 2006, GSI Technology 11 CQ DQ3 NC NC DQ2 DQ0 TDI ...
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... Active Low Input Active High Input Active Low Input — Input — Input — Output — Input — Input — Input/Output Three State Input Active Low Output — Output — Supply 1.8 V Nominal Supply 1.5 V Nominal Supply — © 2006, GSI Technology ...
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... R/W# low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures data in on the next rising edge of K#, for a total of two transfers per address load. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 7/37 © 2006, GSI Technology ...
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... KHKH Power-Up Sequence (Doff controlled) Power-Up Sequence (Doff tied High) Stop Clock Interval 30ns Min 8/37 ). KCVar DLL Locking Interval (1024 Cycles) Normal Operation DLL Locking Interval (1024 Cycles) Normal Operation © 2006, GSI Technology ...
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... RAM to function as a conventional pipelined read SRAM. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 BW1 D0–D8 1 Data In 0 Don’t Care Byte 4 D9–D17 Written Beat 2 9/37 D9–D17 Don’t Care Data In © 2006, GSI Technology ...
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... Example Four Bank Depth Expansion Schematic R/W A – Bank R – Note: For simplicity BWn (or NWn), K, and C are not shown. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 Bank 1 Bank R/W R 10/37 Bank R © 2006, GSI Technology ...
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... The output driver is implemented with discrete binary weighted impedance steps. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 11/37 © 2006, GSI Technology ...
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... Dx stored if BWn = 0 in both data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer 12/37 Operation Hi-Z Deselect D@K Write n+1 Q@K n+2 or Read C n ↑ n © 2006, GSI Technology D ↑ ...
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... GS8342T08/09/18/36AE-333/300/250/200/167 Current Operation K ↑ Write Dx stored if NWn = 0 in both data transfers Write Dx stored if NWn = 0 in 1st data transfer only Write Dx stored if NWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer 13/ ↑ ↑ n+1 n © 2006, GSI Technology ...
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... Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Data In Data In Data In Data In Data In Data In Data In Data In © 2006, GSI Technology ...
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... LD = Low, “LOAD” refers to read new address inactive status with LD = High. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 B2 State Diagram Power-Up LOAD NOP LOAD Load New Address READ 15/37 LOAD WRITE LOAD DDR Write © 2006, GSI Technology ...
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... V max.) DDQ +/–100 mA dc +/–100 125 o –55 to 125 Typ. Max. Unit 1.8 1.9 — 1.9 — 0.95 ≤ 1.6 V (i.e., 1.5 V I/O) DDQ , followed by signal inputs. The DD DDQ REF Typ. Max. Unit © 2006, GSI Technology °C °C ...
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... Max Units – 0.10 V REF levels are defined separately for measuring timing parame- Min Max Units + 0.20 — – 0.20 — V REF 5% V (DC) — V REF . REF Overshoot Measurement and Timing 20% tKHKH 50 © 2006, GSI Technology Notes 1 1 Notes 3,4 3,4 1 ...
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... RQ = 250 Ω (HSTL I/O) V REF 50Ω DDQ Symbol Test Conditions ≥ V ≥ INDOFF 0 V ≤ V ≤ Output Disable OUT DDQ 18/37 Typ. Max Conditions V DDQ V/ DDQ V /2 DDQ = 0.75 V Min. Max Notes – –100 – – © 2006, GSI Technology Unit ...
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... GSI Technology Notes Notes –40 to 85°C 510 460 410 410 210 ...
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... GSI Technology Units cycle ...
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... DD 21/37 -200 -167 Max Min Max Min Max — 0.6 — 0.7 — — 0.6 — 0.7 — — 0.4 — 0.5 — and input clock are stable. © 2006, GSI Technology Units ...
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... Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 22/37 © 2006, GSI Technology ...
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... Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 23/37 © 2006, GSI Technology ...
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... Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 24/37 © 2006, GSI Technology ...
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... Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 25/37 © 2006, GSI Technology ...
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... RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 TDO should be left unconnected Description 26/37 . The JTAG output DD © 2006, GSI Technology ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 27/37 · · TDO © 2006, GSI Technology ...
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... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 Not Used 28/37 GSI Technology JEDEC Vendor ID Code © 2006, GSI Technology 0 1 ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 29/37 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2006, GSI Technology ...
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... Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 Description 30/37 Notes © 2006, GSI Technology ...
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... V /2 DDQ V /2 DDQ 31/37 Min. Max. Unit Notes 0 –0 –300 –1 100 uA – – 200 mV — — 0 – 100 mV — 100 mV V — JTAG Port AC Test Load DQ 50Ω DDQ * Distributed Test Jig Capacitance © 2006, GSI Technology 30pF ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit 50 — ns — — — — — ns 32/37 tTKL tTKL © 2006, GSI Technology ...
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... Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8342T08/09/18/36AE-333/300/250/200/167 BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 15±0.05 B 0.20(4x) 33/37 A1 CORNER 1.0 © 2006, GSI Technology ...
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... BGA 250 165-Pin BGA 200 165-Pin BGA 167 165-Pin BGA 333 165-Pin BGA 300 165-Pin BGA 250 165-Pin BGA 200 165-Pin BGA 167 165-Pin BGA 333 165-Pin BGA 300 165-Pin BGA 250 165-Pin BGA 200 © 2006, GSI Technology ...
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... Ordering Information—GSI SigmaCIO DDR-II SRAM Org Part Number1 GS8342T18AE-167I GS8342T36AE-333 GS8342T36AE-300 GS8342T36AE-250 GS8342T36AE-200 GS8342T36AE-167 GS8342T36AE-333I GS8342T36AE-300I GS8342T36AE-250I GS8342T36AE-200I GS8342T36AE-167I GS8342T08AGE-333 GS8342T08AGE-300 GS8342T08AGE-250 GS8342T08AGE-200 GS8342T08AGE-167 GS8342T08AGE-333I GS8342T08AGE-300I GS8342T08AGE-250I GS8342T08AGE-200I GS8342T08AGE-167I GS8342T09AGE-333 GS8342T09AGE-300 GS8342T09AGE-250 GS8342T09AGE-200 GS8342T09AGE-167 GS8342T09AGE-333I GS8342T09AGE-300I GS8342T09AGE-250I GS8342T09AGE-200I GS8342T09AGE-167I Notes: 1. For Tape and Reel add the character “ ...
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... RoHS-compliant 165-Pin BGA SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA SigmaCIO DDR-II B2 SRAM RoHS-compliant 165-Pin BGA 36/37 Speed Package (MHz) 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 © 2006, GSI Technology ...
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... Added Power-up sequence section Content • Added CZ operating current numbers • Changed status to PQ Content • Added V note to Pin Description table REF Content • Updated FLXDrive-II Output Driver Impedance Control section • Removed Preliminary banner due to production status 37/37 Revisions © 2006, GSI Technology ...