M29W800AT90M1 Micron Technology Inc, M29W800AT90M1 Datasheet - Page 12

• Manufacturer Part Number: M29W800AT90M1
• Manufacturer: Micron Technology Inc

Specifications of M29W800AT90M1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SO
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Supplier Unconfirmed

M29W800AT, M29W800AB
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command se-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security. In-
structions are initialised by two initial Coded cycles
which unlock the Command Interface. In addition,
for Erase, instruction confirmation is again preced-
ed by the two Coded cycles.
See
mands.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address AAAh in the
Byte-wide configuration and at address 555h in
the Word-wide configuration during the first cycle.
During the second cycle the Coded cycles consist
of writing the data 55h at address 555h in the Byte-
wide configuration and at address 2AAh in the
Word-wide configuration. In the Byte-wide config-
uration the address lines A–1 to A10 are valid, in
Word-wide A0 to A11 are valid, other address lines
are 'don't care'. The Coded cycles happen on first
and second cycles of the command write or on the
fourth and fifth cycles.
Table 7. Commands
12/40
Hex Code
Table 7., Commands
A0h
B0h
F0h
00h
10h
20h
30h
80h
90h
Invalid/Reserved
Chip Erase Confirm
Reserved
Block Erase Resume/Confirm
Set-up Erase
Read Electronic Signature/
Block Protection Status
Program
Erase Suspend
Read Array/Reset
for a summary of Com-
Command
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. A wait state of 10µs is nec-
essary after Read/Reset prior to any valid read if
the memory was in an Erase mode when the RD
instruction is given. The Read/Reset command is
not accepted during Erase and erase Suspend.
Auto Select (AS) Instruction. This
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAh in
the Byte-wide configuration or address 555h in the
Word-wide configuration for command set-up. A
subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code, 20h, is output when the ad-
dresses lines A0 and A1 are Low, the device code,
EEh for Top Boot, EFh for Bottom Boot is output
when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction,
A0 is set to V
fine the address of the block to be verified. A read
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to address AAAh in the
Byte-wide configuration or to address 555h in the
Word-wide configuration on the third cycle after
two Coded cycles. A fourth write operation latches
the Address on the falling edge of W or E and the
Data to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing '0' in place of
'1'. Status bits DQ6 and DQ7 determine if pro-
gramming is on-going and DQ5 allows verification
of any possible error. Programming at an address
not in blocks being erased is also possible during
erase suspend. In this case, DQ2 will toggle at the
address being programmed.
Block Erase (BE) Instruction. This
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh
in the Byte-wide configuration or address 555h in
the Word-wide configuration on third cycle after
the two Coded cycles. The Block Erase Confirm
command 30h is similarly written on the sixth cycle
after another two Coded cycles. During the input of
the second command an address within the block
to be erased is given and latched into the memory.
Additional block Erase Confirm commands and
IL
with A1 at V
IH
, while A12-A18 de-
instruction
instruction