M29W800AT90M1 Micron Technology Inc, M29W800AT90M1 Datasheet - Page 13

• Manufacturer Part Number: M29W800AT90M1
• Manufacturer: Micron Technology Inc

Specifications of M29W800AT90M1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SO
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Supplier Unconfirmed

block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. The erase will start after the erase tim-
eout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for oth-
er blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is '0'
the Block Erase Command has been given and
the timeout is running, if DQ3 is '1', the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or E output the status register status
bits.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction. Data Polling bit DQ7 returns '0' while
the erasure is in progress and '1' when it has com-
pleted. The Toggle bit DQ2 and DQ6 toggle during
the erase operation. They stop when erase is com-
pleted. After completion the Status Register bit
DQ5 returns '1' if there has been an erase failure.
In such a situation, the Toggle bit DQ2 can be
used to determine which block is not correctly
erased. In the case of erase failure, a Read/Reset
RD instruction is necessary in order to reset the P/
E.C.
Chip Erase (CE) Instruction. This
uses six write cycles. The Erase Set-up command
80h is written to address AAAh in the Byte-wide
configuration or the address 555h in the Word-
wide configuration on the third cycle after the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after an-
other two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy-
instruction
cles are wrong, the instruction aborts and the de-
vice is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh.
Read operations after the sixth rising edge of W or
E output the Status Register bits. During the exe-
cution of the erase by the P/E.C., Data Polling bit
DQ7 returns '0', then '1' on completion. The Toggle
bits DQ2 and DQ6 toggle during erase operation
and stop when erase is completed. After comple-
tion the Status Register bit DQ5 returns '1' if there
has been an Erase Failure.
Erase Suspend (ES) Instruction. The
Erase operation may be suspended by this in-
struction which consists of writing the command
B0h without any specific address. No Coded cy-
cles are required. It permits reading of data from
another block and programming in another block
while an erase operation is in progress. Erase sus-
pend is accepted only during the Block Erase in-
struction execution. Writing this command during
Erase timeout will, in addition to suspending the
erase, terminate the timeout. The Toggle bit DQ6
stops toggling when the P/E.C. is suspended. The
Toggle bits will stop toggling between 0.1µs and
15µs after the Erase Suspend (ES) command has
been written. The device will then automatically be
set to Read Memory Array mode. When erase is
suspended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at '1'. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data is being programmed.
Erase Resume (ER) Instruction. If
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
M29W800AT, M29W800AB
an
Erase
Block
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