GS84118AT-100 GSI TECHNOLOGY, GS84118AT-100 Datasheet

GS84118AT-100

Manufacturer Part Number

GS84118AT-100

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS84118AT-100.pdf (20 pages)

Specifications of GS84118AT-100

Density

4.5Mb

Access Time (max)

12ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

66.7MHz

Operating Supply Voltage (typ)

3.3V

Address Bus

18b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

140mA

Operating Supply Voltage (min)

3.135V

Operating Supply Voltage (max)

3.6V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

18b

Number Of Words

256K

Lead Free Status / Rohs Status

Not Compliant

Available stocks

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Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

GS84118AT-100

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MAXIM

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TQFP, BGA

Commercial Temp

Industrial Temp

Features

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• Intergrated data comparator for Tag RAM application

• FT mode pin for flow through or pipeline operation

• LBO pin for Linear or Interleave (Pentium

• Synchronous address, data I/O, and control inputs

• Synchronous Data Enable (DE)

• Asynchronous Output Enable (OE)

• Asynchronous Match Output Enable (MOE)

• Byte Write (BWE) and Global Write (GW) operation

• Three chip enable signals for easy depth expansion

• Internal self-timed write cycle

• JTAG Test mode conforms to IEEE standard 1149.1

• JEDEC-standard 100-lead TQFP and 119-BGA packages

• Pb-Free 100-lead TQFP package available

Functional Description

The GS84118A is a 256K x 18 high performance synchronous

SRAM with integrated Tag RAM comparator. A 2-bit burst

counter is included to provide burst interface with Pentium

and other high performance CPUs. It is designed to be used as

a Cache Tag SRAM, as well as data SRAM. Addresses, data

IOs, match output, chip enables (CE1, CE2, CE3), address

control inputs (ADSP, ADSC, ADV), and write control inputs

(BW1, BW2, BWE, GW, DE) are synchronous and are

controlled by a positive-edge-triggered clock (CLK).

Output Enable (OE), Match Output Enable, and power down

control (ZZ) are asynchronous. Burst can be initiated with

either ADSP or ADSC inputs. Subsequent burst addresses are

generated internally and are controlled by ADV. The burst

sequence is either interleave order (Pentium

linear order, and is controlled by LBO.

Rev: 1.02 4/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel

mode

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

and X86) Burst

or x86) or

cycle

256K x 18 Sync

Parameter Synopsis

Cache Tag

1/20

310 mA

190 mA

6.0 ns

3.5 ns

8.5 ns

10 ns

-166

275 mA

190 mA

Output registers and the Match output register are provided and

controlled by the FT mode pin (Pin 14). Through use of the FT

mode pin, I/O registers can be programmed to perform pipeline

or flow through operation. Flow Through mode reduces

latency.

Byte write operation is performed by using Byte Write Enable

(BWE) input combined with two individual byte write signals

BW1-2. In addition, Global Write (GW) is available for

writing all bytes at one time.

Compare cycles begin as a read cycle with output disabled so

that compare data can be loaded into the data input register.

The comparator compares the read data with the registered

input data and a match signal is generated. The match output

can be either in Pipeline or Flow Through modes controlled by

the FT signal.

Low power (Standby mode) is attained through the assertion of

the ZZ signal, or by stopping the clock (CLK). Memory data is

retained during Standby mode.

JTAG boundary scan interface is provided using IEEE

standard 1149.1 protocol. Four pins—Test Data In (TDI), Test

Data Out (TDO), Test Clock (TCK) and Test Mode Select

(TMS)—are used to perform JTAG function.

The GS84118A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V or 2.5 V LVTTL-compatible.

Separate output (V

2.5 V IO interface.

* Pentium is a trademark of Intel Corp.

6.6 ns

3.8 ns

10 ns

-150

250 mA

140 mA

7.5 ns

4.0 ns

11 ns

15 ns

-133

DDQ

190 mA

140 mA

4.5 ns

10 ns

12 ns

15 ns

GS84118AT/B-166/150/130/100

-100

) pins are used to allow both 3.3 V or

3.3 V and 2.5 V I/O

166 MHz–100 MHz

3.3 V V

Related parts for GS84118AT-100

GS84118AT-100 Summary of contents

Page 1

... KQ 310 mA 275 mA 250 8 cycle 190 mA 190 mA 140 1/20 GS84118AT/B-166/150/130/100 166 MHz–100 MHz 3 3.3 V and 2.5 V I/O ) pins are used to allow both 3 DDQ -100 10 ns 4.5 ns 190 140 mA © 2001, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DDQ Rev: 1.02 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84118AT/B-166/150/130/100 Pin Configuration 256K x 18 Top View 2/ DDQ VDDQ DDQ DDQ 53 MATCH DE 52 MOE 51 © 2001, GSI Technology ...

Page 3

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 84118A PadOut—119-Bump BGA—Top View ADSP DDQ ADSC DDQ ADV DDQ DDQ LBO TMS TDI TCK DDQ 3/20 GS84118AT/B-166/150/130/100 DDQ DDQ DDQ MATCH V SS DDQ MOE TDO NC V DDQ © 2001, GSI Technology ...

Page 4

... Power down control—Application of ZZ will result in a low standby power consumption. Flow Through or Pipeline mode Linear Order Burst mode Test Mode Select 3.3 V power supply 2.5 V/3.3 V output power supply 4/20 GS84118AT/B-166/150/130/100 Chip Enables Output Enable Match Output Test Data In Test Data Out Test Clock ...

Page 5

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Functional Block Diagram INARY OUNTER Load Register D Q Register D Q Register D Q Register D Q Register D Q TDO 5/20 GS84118AT/B-166/150/130/100 18 A 256K 18 X Memory Array DQ1–DQ16 Match DQP1–DQP2 © 2001, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ZZ Function Active H Standby, IDD = ISB 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address BW1 BW2 6/20 GS84118AT/B-166/150/130/100 FT Function L Flow Through Pipeline Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1: © 2001, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Address Used CE1 CE2 CE3 ADSP none none none none none external external external external external next next next next next next current current current current current current 7/20 GS84118AT/B-166/150/130/100 ADSC ADV Write OE CLK ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. DE MOE Commerical –0.5 to 4.6 –0 –0 –0 0.5 DD (≤ 4.6 V max. ) –0 0.5 DD (≤ 4.6 V max. ) +/–20 1 –55 to 125 8/20 GS84118AT/B-166/150/130/100 OE Match DQ L — — Data Out D X — High High Z X High Z High Z Unit © 2001, GSI Technology ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Layer Board Symbol R single ΘJA R four ΘJA R — ΘJC Conditions V/ns 1.25 V 1.25 V Fig. 1& OHZ 9/20 GS84118AT/B-166/150/130/100 TQFP max PBGA max Unit °C °C °C Output load 1 DQ 50W 30pF Output load 2 2.5 V 225W DQ 1 225W ...

Page 10

... Test Conditions ≥ V ≥ ≤ V ≤ ≥ V ≥ ≤ V ≤ Output Disable OUT –4 mA 2.375 DDQ I = –4 mA 3.135 DDQ 10/20 GS84118AT/B-166/150/130/100 Min Max – – –1 uA 300 uA –30 0uA 1 uA – – 1.7 V 2.4 V 0.4 V © 2001, GSI Technology ...

Page 11

... I DD 310 320 Pipeline 190 200 Flow Through Pipeline Flow Through I DD 110 120 Pipeline Flow Through 11/20 GS84118AT/B-166/150/130/100 -150 -133 -100 0 –40 0 – 70°C +85°C 70°C +85°C 70°C 275 285 250 260 190 190 200 140 150 140 ...

Page 12

... GS84118AT/B-166/150/130/100 -133 -100 Unit Min Max Min Max 7.5 — 10 — ns — 4 — 4.5 ns 1.5 — 1.5 — ns 1.5 — 1.5 — ...

Page 13

... ADSC initiated read and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 13/20 GS84118AT/B-166/150/130/100 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2001, GSI Technology Deselect tKQX ...

Page 14

... Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 14/20 GS84118AT/B-166/150/130/100 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2001, GSI Technology tKQX ...

Page 15

... Address MOE tKM tMOE tMLZ Match Rev: 1.02 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pipeline Compare Fill Write Cycle Miss B A tKM tKMX 15/20 GS84118AT/B-166/150/130/100 Fill Write B tKM © 2001, GSI Technology ...

Page 16

... DE MOE tKM tMOE tMLZ Match Rev: 1.02 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Flow Through Compare Fill Write Cycle Miss B A tKM tKMX 16/20 GS84118AT/B-166/150/130/100 Fill Write B tKM © 2001, GSI Technology ...

Page 17

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — 22.0 22.1 e 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0. 0° — 7° 17/20 GS84118AT/B-166/150/130/100 E1 E © 2001, GSI Technology ...

Page 18

... Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.02 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84118AT/B-166/150/130/100 BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) 18/ 1.27 © 2001, GSI Technology ...

Page 19

... GS84118AT-150 256K x 18 GS84118AT-133 256K x 18 GS84118AT-100 256K x 18 GS84118AT-166I 256K x 18 GS84118AT-150I 256K x 18 GS84118AT-133I 256K x 18 GS84118AT-100I 256K x 18 GS84118AGT-166 256K x 18 GS84118AGT-150 256K x 18 GS84118AGT-133 256K x 18 GS84118AGT-100 256K x 18 GS84118AGT-166I 256K x 18 GS84118AGT-150I 256K x 18 ...

Page 20

... Updated format • Updated mechanical drawings Format/Content • Updated timing diagrams • Added Pb-free info for TQFP • Added Pipeline Compare Fill Write Cycle and Flow Through Content Compare Fill Write Cycle timing diagrams 20/20 GS84118AT/B-166/150/130/100 © 2001, GSI Technology ...

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