PPC440GX-3NF533C Applied Micro Circuits Corporation, PPC440GX-3NF533C Datasheet - Page 5

• Manufacturer Part Number: PPC440GX-3NF533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF533C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

Revision 1.20 – June 9, 2009
PPC440GX Functional Block Diagram
The PPC440GX is designed using the IBM
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus
Note: IBM CoreConnect buses provide:
Address Maps
The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GX processor through the use of mtdcr and mfdcr instructions.
AMCC
Data Sheet
• 128-bit PLB interfaces up to 166 MHz
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
63 internal
18 external
Controller
Universal
Interrupt
Control
Reset
Clock
Messaging
D-Cache
32KB
JTAG
I2O
Processor Core
L2 Controller
PPC440
Timers
133MHz max
32/64-bit data
Processor Local Bus (PLB)
MMU
I-Cache
32KB
Trace
Power
Mgmt
Bridge
PCI-X
®
13-bit addr
166MHz max
32/64-bit data
Microelectronics Blue Logic
256KB
SRAM
Arb
DCR Bus
DDR SDRAM
DCRs
440GX – Power PC 440GX Embedded Processor
Controller
(4-Channel)
Controller
DMA
MAL
1 GMII
or
2 RGMII
or
1 TBI
or
2 RTBI
Timers
On-chip Peripheral Bus (OPB)
GP
™
1000 x2
10/100/
Architecture.
Bridge
RGMII
Bridge
OPB
™
TAH
methodology in which major functional
Ethernet
GPIO
10/100
Bridge
ZMII
x2
1 MII
or
2 RMII
or
4 SMII
IIC
x2
Bus Master
Controller
External
UART
83MHz max
32-bit addr
32-bit data
x2
Controller
External
Bus
5