PPC440GX-3NF533C Applied Micro Circuits Corporation, PPC440GX-3NF533C Datasheet - Page 50

• Manufacturer Part Number: PPC440GX-3NF533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF533C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

440GX – Power PC 440GX Embedded Processor
50
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ to GND)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to 3.3V) or pull-down (recommended value is 1kΩ to GND)
PCIXTRDY
DDR SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn0:3
DM0:8
DQS0:8
ECC0:7
MemAddr00:12
MemClkOut0
MemClkOut0
MemData00:63
MemVRef1:2
RAS
WE
Ethernet Interface
EMCCD,
EMC1RxErr,
GMCGTxClk,
GMC0TxClk,
TBITxClk,
RTBI0TxClk
EMCCrS,
EMC0CrSDV,
GMCTxD7,
GMC1TxD3,
TBITxD7,
RTBI1TxD3
EMCMDClk
EMCMDIO
required
Signal Name
I
phase of the transaction.
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Clock Enable. One for each bank.
Memory write data byte lane masks. MEMDM8 is the byte lane
mask for the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the ECC byte
lane.
ECC check bits 0:7.
Memory address bus.
Subsystem clock.
Memory data bus.
Memory reference voltage (SV
Row Address Strobe.
Write Enable.
MII: Collision detection
RMII 1: Receive error
GMII: 1000Mbps Transmit clock
RGMII: Transmit clock
TBI: Transmit clock
RTBI: Transmit clock
MII: Carrier sense
RMII 0: Carrier sense data valid
GMII: Transmit data
RGMII 1: Transmit data
TBI: Transmit data
RTBI 1: Transmit data
MII and RMII: Management data clock
MII and RMII: Transfer command and status information between
MII and PHY
ndicates the target agent’s ability to complete the current data
(Sheet 2 of 8)
Description
REF
) input.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 1.20 – June 9, 2009
O
O
O
O
O
O
O
O
O
O
I
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
Voltage Ref
3.3V PCI
Receiver
Type
Data Sheet
Notes
4
AMCC