GS880Z36BT-250 GSI TECHNOLOGY, GS880Z36BT-250 Datasheet

GS880Z36BT-250

Manufacturer Part Number

GS880Z36BT-250

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS880Z36BT-250.pdf (24 pages)

Specifications of GS880Z36BT-250

Density

9Mb

Access Time (max)

5.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

181.8MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

18b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

160mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

256K

Lead Free Status / Rohs Status

Not Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS880Z18/32/36BT is a 9Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Rev: 1.04b 11/2010

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Flow Through

Pipeline

3-1-1-1

2-1-1-1

9Mb Pipelined and Flow Through

Curr (x32/x36)

Curr (x18)

Synchronous NBT SRAM

tCycle

Paramter Synopsis

1/24

-333

250

290

200

230

2.5

3.0

4.5

-300

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS880Z18/32/36BT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

The GS880Z18/32/36BT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

230

265

185

210

2.5

3.3

5.0

-250

200

230

160

185

GS880Z18/32/36BT-333/300/250/200/150

2.5

4.0

5.5

-200

170

195

140

160

3.0

5.0

6.5

-150

140

160

128

145

3.8

6.7

7.5

Unit

333 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS880Z36BT-250

GS880Z36BT-250 Summary of contents

Page 1

... Curr (x18) 200 185 160 Curr (x32/x36) 230 210 185 1/24 333 MHz–150 MHz 3.3 V I/O -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 170 140 mA 195 160 mA 6.5 7.5 ns 6.5 7.5 ns 140 128 mA 160 145 mA © 2001, GSI Technology DD ...

Page 2

... Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18BT 100-Pin TQFP Pinout (Package T) 512K x 18 Top View These pins can also be left floating 2/24 GS880Z18/32/36BT-333/300/250/200/150 DDQ DQP DDQ DDQ DDQ © 2001, GSI Technology A ...

Page 3

... Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z32BT 100-Pin TQFP Pinout (Package T) 256K x 32 Top View These pins can also be left floating 3/24 GS880Z18/32/36BT-333/300/250/200/150 DDQ DDQ DDQ DDQ © 2001, GSI Technology ...

Page 4

... DQP Note: Pins marked with NC can be tied to either V Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z36BT 100-Pin TQFP Pinout (Package T) 256K x 36 Top View These pins can also be left floating 4/24 GS880Z18/32/36BT-333/300/250/200/150 ...

Page 5

... Data I/O Pin; Byte B 9th Data I/O Pin; Byte C 9th Data I/O Pin; Byte D Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply No Connect 5/24 © 2001, GSI Technology ...

Page 6

... GS880Z18/32/36B NBT SRAM Functional Block Diagram Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18/32/36BT-333/300/250/200/150 Amps Sense Drivers Write 6/24 © 2001, GSI Technology ...

Page 7

... Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated. A write C, D 7/24 GS880Z18/32/36BT-333/300/250/200/150 , E and E ). Deassertion of any one of the Enable © 2001, GSI Technology ...

Page 8

... Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18/32/36BT-333/300/250/200/150 State Diagram Key 8/24 ADSP ADSC ADV © 2001, GSI Technology 3 DQ High-Z High-Z High-Z High-Z High ...

Page 9

... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 9/24 New Write Burst Write B D n+3 ƒ ƒ © 2001, GSI Technology ...

Page 10

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 10/24 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2001, GSI Technology ...

Page 11

... Pipeline and Flow Through Read Write Control State Diagram 11/24 GS880Z18/32/36BT-333/300/250/200/150 R B Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2001, GSI Technology ...

Page 12

... Note: The burst counter wraps to initial state on the 5th clock. 12/24 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: © 2001, GSI Technology ...

Page 13

... Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18/32/36BT-333/300/250/200/150 Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 13/24 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 2001, GSI Technology ...

Page 14

Page 15

... Overshoot Measurement and Timing not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Symbol Test conditions I/O OUT 15/24 Typ. Max. Unit V + 0.3 — 0.3*V V — DD Typ. Max. Unit 25 70 ° °C 50% tKC Typ. Max. Unit © 2001, GSI Technology ...

Page 16

... Output Disable –8 mA, V OH2 –8 mA, V OH3 16/24 Conditions V – DDQ Fig Min – ≥ V – ≤ V – ≥ V –100 ≤ V – –1 uA OUT DD = 2.375 V 1.7 V DDQ = 3.135 V 2.4 V DDQ — © 2001, GSI Technology Max 100 — — 0.4 V ...

Page 17

... GSI Technology -150 –40 Unit to 85°C 160 mA 20 150 mA 15 150 mA 10 140 ...

Page 18

... GSI Technology Unit ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18/32/36BT-333/300/250/200/150 Pipeline Mode Timing (NBT) Suspend Read C Write D Write No-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 19/24 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2001, GSI Technology ...

Page 20

... Flow Through Mode Timing (NBT) Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 20/24 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE © 2001, GSI Technology tKQX D(G) ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18/32/36BT-333/300/250/200/150 θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7° — 21/ © 2001, GSI Technology ...

Page 22

... GS880Z32BT-300I 256K x 32 GS880Z32BT-250I 256K x 32 GS880Z32BT-200I 256K x 32 GS880Z32BT-150I 256K x 36 GS880Z36BT-333I 256K x 36 GS880Z36BT-300I 256K x 36 GS880Z36BT-250I 256K x 36 GS880Z36BT-200I 256K x 36 GS880Z36BT-150I 512K x 18 GS880Z18BGT-333 512K x 18 GS880Z18BGT-300 512K x 18 GS880Z18BGT-250 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880Z18BT-150IT. ...

Page 23

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.04b 11/2010 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 24

... Changed Pb-free to RoHS-compliant Content/Format • (Rev 1.03a: Corrected label on x32 pinout) • Added note to pinouts (pg • Rev.1.04a: Revised Designing for Compatibility section Content • (Rev1.04b: Updated Abs Max section (under/overshoot note); removed status column from ordering info table) 24/24 © 2001, GSI Technology ...

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