GS8320Z36T-133 GSI TECHNOLOGY, GS8320Z36T-133 Datasheet

GS8320Z36T-133

Manufacturer Part Number
GS8320Z36T-133
Description
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS8320Z36T-133

Density
36Mb
Access Time (max)
8.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
117.6MHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
20b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
4
Supply Current
160mA
Operating Supply Voltage (min)
2.3/3V
Operating Supply Voltage (max)
2.7/3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
1M
Lead Free Status / Rohs Status
Not Compliant
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.03d 1/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
Through
Pipeline
3-1-1-1
2-1-1-1
36Mb Pipelined and Flow Through
Flow
Synchronous NBT SRAMs
Curr
Curr
Curr
Curr
tCycle
tCycle
t
t
(x32/x36)
(x32/x36)
KQ
KQ
(x18)
(x18)
Parameter Synopsis
1/23
-250 -225 -200 -166 -150 -133 Unit
285
350
205
235
2.5
4.0
6.5
6.5
265
320
195
225
2.7
4.4
7.0
7.0
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
245
295
185
210
3.0
5.0
7.5
7.5
220
260
175
200
3.5
6.0
8.0
8.0
GS8320Z18/36T-250/225/200/166/150/133
210
240
165
190
3.8
6.6
8.5
8.5
185
215
155
175
4.0
7.5
8.5
8.5
mA
mA
mA
mA
ns
ns
ns
ns
© 2001, GSI Technology
250 MHz–133 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS8320Z36T-133

GS8320Z36T-133 Summary of contents

Page 1

... Curr 205 195 185 175 (x18) Curr 235 225 210 200 (x32/x36) 1/23 250 MHz–133 MHz 3.3 V I/O 3.8 4.0 ns 6.6 7.5 ns 210 185 mA 240 215 mA 8.5 8.5 ns 8.5 8.5 ns 165 155 mA 190 175 mA © 2001, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DQP DDQ Rev: 1.03d 1/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 GS8320Z18T Pinout Top View 2/ DDQ DQP DDQ DDQ DDQ © 2001, GSI Technology ...

Page 3

... DQP DDQ DDQ DDQ DDQ DQP Rev: 1.03d 1/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 GS8320Z36T Pinout Top View 3/23 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2001, GSI Technology ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply No Connect 4/23 ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 2001, GSI Technology ...

Page 5

... GS8320Z18/36 NBT SRAM Functional Block Diagram Rev: 1.03d 1/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/23 © 2001, GSI Technology ...

Page 6

... Rev: 1.03d 1/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 & determine which bytes will be written. All or none may be activated. A write and E ). Deassertion of any one of the Enable © 2001, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Address CK CKE ADV W External L Next L External L Next L External L None L Next L Next L None L None L None L None L None Current L 7/ High High High High High High High High High © 2001, GSI Technology Notes 1,10 2 1,2, 1,3,10 1,2,3, ...

Page 8

... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 8/23 New Write Burst Write B D n+3 ƒ ƒ © 2001, GSI Technology ...

Page 9

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/23 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2001, GSI Technology ...

Page 10

... Pipeline and Flow Through Read Write Control State Diagram 10/ Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2001, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/23 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: © 2001, GSI Technology ...

Page 12

... Rev: 1.03d 1/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 12/23 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 2001, GSI Technology ...

Page 13

... V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Min. Typ. Max. 3.0 3.3 3.6 2.3 2.5 2.7 3.0 3.3 3.6 2.3 2.5 2.7 Min. Typ. Max 0.3 2.0 — DD –0.3 — 0.8 © 2001, GSI Technology Unit Unit Unit V V ...

Page 14

... Overshoot Measurement and Timing not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Symbol Test conditions I/O OUT 14/23 Typ. Max. Unit V + 0.3 — 0.3*V V — DD Typ. Max. Unit 25 70 ° °C 20% tKC Typ. Max. Unit © 2001, GSI Technology ...

Page 15

... Output Disable –8 mA, V OH2 –8 mA, V OH3 15/23 Conditions V – DDQ Fig Min – ≥ V – ≤ V – ≥ V –100 ≤ V – –1 uA OUT DD = 2.375 V 1.7 V DDQ = 3.135 V 2.4 V DDQ — © 2001, GSI Technology Max 100 — — 0.4 V ...

Page 16

... Rev: 1.03d 1/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18//36T-250/225/200/166/150/133 16/23 © 2001, GSI Technology ...

Page 17

... GSI Technology -133 Unit Min Max 7.5 ns — — 4.0 ns 1.5 ns — 1.5 — ns 1.5 ns — 0.5 — ns 8.5 ns — — 8 ...

Page 18

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Pipeline Mode Timing (NBT) Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 18/23 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2001, GSI Technology ...

Page 19

... Flow Through Mode Timing (NBT) Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 19/23 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE © 2001, GSI Technology tKQX D(G) ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 TQFP Package Drawing (Package T) θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7° — 20/ © 2001, GSI Technology ...

Page 21

... GS8320Z18T-150I GS8320Z18T-133I GS8320Z36T-250I GS8320Z36T-225I GS8320Z36T-200I GS8320Z36T-166I GS8320Z36T-150I GS8320Z36T-133I GS8320Z18GT-250 GS8320Z18GT-225 GS8320Z18GT-200 GS8320Z18GT-166 GS8320Z18GT-150 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 22

... GS8320Z36GT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 23

... Updated DC Electrical Characteristics table • Removed Output Load 2 diagram on page 15 • Updated format • Added RoHS-compliant information for TQFP package • (Rev 1.03c: Removed Preliminary banner due to production Content/Format status) • Rev 1.03d: Updated TQFP pinout 23/23 © 2001, GSI Technology ...

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