DT28F160F3T95 Intel, DT28F160F3T95 Datasheet - Page 10

• Manufacturer Part Number: DT28F160F3T95
• Manufacturer: Intel

Specifications of DT28F160F3T95

• Density: 16Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F800F3—Automotive
4
A
DQ
DQ
CLK
ADV#
CE#
RST#
OE#
0
Sym
–
A
0
15
Figure 2. SSOP Pinout
Table 1.
–
19
8-Mbit
WAIT#
ADV#
GND
GND
DQ
DQ
GND
DQ
DQ
V
CLK
DQ
DQ
DQ
DQ
V
V
CCQ
NC
A
A
A
A
A
A
NC
A
INPUT
INPUT/
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
A
A
CC
CC
15
14
13
12
11
10
14
15
16
13
12
9
8
6
7
5
4
Type
NOTE: A
Pin Descriptions (Sheet 1 of 2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
--A
--A
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally
latched during read and write cycles.
8-Mbit: A
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during memory
array, status register (DQ
when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle.
CLOCK: Synchronizes the flash memory to the system operating frequency during synchronous burst
mode read operations. When configured for synchronous burst-mode reads, the address is latched on
the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV#
is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous
page-mode read and write operations.
ADDRESS VALID: Indicates that a valid address is present on the address inputs. Addresses are
latched on the rising edge of ADV# during read and write operations. ADV# may be tied active during
asynchronous read and write operations.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RESET: When driven low, RST# inhibits write operations which provides data protection during power
transitions, and it resets internal automation. RST#-high enables normal operation. Exit from reset sets
the device to asynchronous read array mode.
OUTPUT ENABLE: Gates data outputs during a read cycle.
20
20
21
and A
32-Mbit
64-Mbit
0–18
21
are the upgrade addresses for potential 32-Mbit and 64-Mbit devices.
0
–
DQ
16 mm x 23.7 mm
56-Lead SSOP
7
TOP VIEW
), and identifier code read cycles. Data pins float to high-impedance
Name and Function
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PRELIMINARY
8-Mbit
WE#
RST#
V
WP#
NC
A
A
A
A
A
A
A
A
A
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
NC
V
DQ
DQ
DQ
DQ
PP
CCQ
1
2
3
4
5
6
7
17
18
0
9
1
8
0
2
10
3
11