DT28F160F3T95 Intel, DT28F160F3T95 Datasheet - Page 17

• Manufacturer Part Number: DT28F160F3T95
• Manufacturer: Intel

Specifications of DT28F160F3T95

• Density: 16Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

4.4
4.5
PRELIMINARY
CLK edge when ADV# is low during synchronous burst mode or the falling edge of OE# or CE#,
whichever occurs first. The Read Status Register command functions independently of the V
voltage.
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be cleared
by issuing the Clear Status Register command. These bits indicate various error conditions. By
allowing system software to reset these bits, several operations may be performed (such as
cumulatively erasing or writing several bytes in sequence). The status register may be polled to
determine if a problem occurred during the sequence. The Clear Status Register command
functions independently of the applied V
returns to read array mode.
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This command sequence requires appropriate
sequencing and address within the block to be erased (erase changes all block data to FFH). Block
preconditioning, erase, and verify are handled internally by the WSM. After the two-cycle block
erase sequence is written, the device automatically outputs status register data when read (see
Figure 7, “Automated Block Erase Flowchart” on page
completion by analyzing status register bit SR.7.
When the block erase completes, check status register bit SR.5 for an error flag (“1”). If an error is
detected, check status register bits SR.4, SR.3, and SR.1 to understand what caused the failure.
After examining the status register, it should be cleared if an error was detected before issuing a
new command. The device will remain in status register read mode until another command is
written to the CUI.
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voltage. After executing this command, the device
20). The CPU can detect block erase
28F800F3—Automotive
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