DT28F160F3T95 Intel, DT28F160F3T95 Datasheet - Page 32

• Manufacturer Part Number: DT28F160F3T95
• Manufacturer: Intel

Specifications of DT28F160F3T95

• Density: 16Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F800F3—Automotive
7.4
7.4.1
7.4.2
7.5
26
System engineers should analyze the breakdown of standby time versus active time and quantify
the respective power consumption in each mode for their specific application. This will provide a
more accurate measure of application-specific power and energy requirements.
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required, since the device is indifferent as to which power supply,
V
RST# Connection
The use of RST# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RST# to
the system reset signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
is active. Since both WE# and CE# must be low for a command write, driving either signal to V
will inhibit writes to the device. The CUI architecture provides additional protection since
alteration of memory contents can only occur after successful completion of the two-step command
sequences. The device is also disabled until RST# is brought to V
control inputs. By holding the device in reset during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another level of memory protection.
V
The CUI latches commands as issued by system software and is not altered by V
transitions or WSM actions. Its default state upon power-up, after exit from deep power-down
mode or after V
After any block erase or program operation is complete (even after V
V
flash memory array is desired.
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device de-coupling. System
designers should consider three supply current issues:
•
•
•
PP
PPLK
CC
, V
Standby current levels (I
Active current levels (I
Transient peaks produced by falling and rising edges of CE#.
, V
CC
), the CUI must be reset to read array mode via the Read Array command if access to the
, or V
PP
and RST# Transitions
CCQ
CC
, powers-up first.
transitions above V
CCR
CCS
)
)
LKO
(Lockout voltage), is read array mode.
CC
voltages are above V
IH
, regardless of the state of its
PP
transitions down to
PP
PRELIMINARY
or CE#
LKO
and V
PP
IH