SA2400ABE NXP Semiconductors, SA2400ABE Datasheet - Page 14

• Manufacturer Part Number: SA2400ABE
• Manufacturer: NXP Semiconductors

Specifications of SA2400ABE

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Not Compliant

1. The 44 MHz common mode digital ground bounce on the I and Q inputs is assumed to be less than –30 dBc relative to signal level.
2. Verified by bench characterization and found to have sufficient margin for production.
3. The power ramping-up delay can be programmed to 2, 3, 4, 5 s. See the 3-wire bus control register map. The default is 2 s.
4. The differential input signal current is the difference between the I and /I (Q and /Q) instantaneous currents. The peak differential current is
1. This is measured at the Output1 RF port with the SA2400A in transmit mode, with static DC offset signals to the transmitter I and Q inputs.
2. The relative output current variation is defined as:
Philips Semiconductors
NOTES:
11. VCO AND SYNTHESIZER
Table 9 lists the synthesizer specifications. The synthesizer has the same specification as the SA8027 fractional PLL main loop without the PHI
speed-up mode. The phase comparator frequency used is typically 4 MHz (in fractional mode). The charge pump current is internally
programmed using the 3-wire bus (Synthesizer Register C). The recommended charge pump current is 480 A. An external reference input of
44 MHz or 22 MHz is supported.
Table 9. Synthesizer and VCO Specifications
T
NOTES:
2002 Nov 04
Specification
IQ input timing
amb
PARAMETER
PARAMETER
VCO
VCO output frequency range
VCO gain (K
Open Loop VCO Phase Noise
External VCO input levels
Main divider
N divider range
Reference divider
Fixed reference input (XTAL_1 and XTAL_2)
f
frequency
R divider range (non-fractional)
Reference input level
Input parallel resistance (XTAL_1, XTAL_2)
Input parallel capacitance (XTAL_1, XTAL_2)
Phase detector
Phase detector frequency
Charge pump
Charge pump current accuracy
Charge pump compliance voltage
Output current variation vs. V
Charge pump sink to source current
Matching
Charge pump “off” current leakage
Single chip transceiver for 2.45 GHz ISM band
therefore (I
The phase detector and divide-by-N phase noise is such that when configured as a phase locked loop with a 30 kHz loop band width, the
phase noise at frequencies between 1 kHz and 30 kHz will be no worse than –80 dBc/Hz. The total closed loop spur power within a 22 MHz
band around the carrier is less than –30 dBc.
with I
= 25 C; V
1
@ V
VCO
max
1
CC
= 0.6 V, I
)
–I
= +3 V
min
)/2 = 500 A.
2
@ V
cp
2
(Note 2)
= V
Conditions
Digital input selected, sampling on falling edge,
relative to REF_CLK_OUT
l i
CC
– 0.7 V (see Figure 4).
REF CLK OUT
TEST CONDITIONS
TEST CONDITIONS
V
Note 1. 1/f
Differential; when device configured for
external VCO
SM = ‘000’
XTAL_1 input
f = 44 MHz; indicative, not tested
f = 44 MHz; indicative, not tested
V
V
V
V
I
tune
cp
cp
cp
cp
I
OUT
ZOUT
= 0.5 V
in compliance range
= 0.5 V
= 0.5 V
= 1.2 V
+ 2
2
CC
CC
CC
roll off region; 0.5 MHz offset
(I
14
I
2
2
* I
) I
1
1
)
Set-up time
Hold time
Min
2.4
70
–
–10
512
–
–
4
350
10
–
–
–20
0.6
–5
–10
–5
Min
–
–
Typ
–
85
–113
–
–
22
44
–
–
–
–
–
–
–
–
–
1
LIMITS
Typ
4
4
Max
2.5
100
–107
0
65535
–
–
1023
1300
–
1.5
4.0
+20
V
+5
+10
5
DD
SA2400A
Max
–
–
0.7
Product data
UNITS
UNITS
GHz
MHz/V
dBc/Hz
dBm
MHz
MHz
mV
k
pF
MHz
%
V
%
%
nA
Units
ns
ns
pp