SA2400ABE NXP Semiconductors, SA2400ABE Datasheet - Page 24

• Manufacturer Part Number: SA2400ABE
• Manufacturer: NXP Semiconductors

Specifications of SA2400ABE

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Not Compliant

Philips Semiconductors
14.4.2 Programming Example
Program synthesizer for 2.412 GHz band
Program synthesizer for 2.462 GHz band
14.6 Fast serial interface AC characteristics
2002 Nov 04
SYMBOL
Serial Bus Logic Level Requirements
V
V
Serial Programming Clock, SCLK
t
t
T
Enable Programming, SEN
T
Data Programming, AGCRESET
T
T
r
f
Input Xtal is 44 MHz, comparison frequency f
reference division ratio R = 11
Target frequency is 2412 MHz, f
N = 603 (no fractional N)
– write this word to register 00: 00 0 000 0000001001011011 00
– write this word to register 01: 00 0000001011 00 1 0 xxxxxxxx
Input Xtal is 44 MHz, comparison frequency f
reference division ratio R = 11
Target frequency is 2462 MHz, f
N = 615.5 (fractional 4/8)
– write this word to register 00: 00 0 100 0000001001100111 00
– write this word to register 01: 00 0000001011 00 1 0 01010000
cyc
on
setup
hold
IH
IL
Single chip transceiver for 2.45 GHz ISM band
(note two leading zeros – unused bits 22, 23)
(x = no significance)
Fractional compensation setting should be set in the application
(depends on the loop parameters) with the help of the SA8027
application note. The nominal value is FC = 640 / FM
(FM = modulus, see address 00).
AGCRESET
SDATA
SCLK
SEN
PARAMETER
PARAMETER
HIGH logic input voltage
LOW logic input voltage
Input rise time
Input fall time
Clock period
Delay to rising clock edge
Input data to clock set-up time
Input data to clock hold time
3–WIRE BUS PROGRAMMING
A0
1
comp
comp
A1
2
= 4 MHz
= 4 MHz
Figure 11. “Fast programming” cycle timing diagram
D23
31
comp
comp
main divider ratio
main divider ratio
= 4 MHz
= 4 MHz
D23
32
TEST CONDITIONS
TEST CONDITIONS
XX
1
D0
T
on
24
D1
2
T
two bits controlling the DC offset cancellation corner frequency can be
14.5 Fast serial interface for Receiver–AGC
programming
When the chip is in mode “FASTTXRXMGC” the internal AGC block
is disabled. Instead, the 10 bits controlling the receiver gain and the
programmed directly via a dedicated second serial interface. This
interface is active when in FASTTXRXMGC mode and when
SEN=HIGH. (SEN acts as a switch between the regular serial
interface and the dedicated bus).
14.5.1 Description of “fast programming” cycle
1. Set the chip to FASTTXRXMGC mode by programming
2. Set the SEN pin to HIGH.
3. With each rising edge on pin SCLK, a new data bit is expected at
4. With the 12
5. The regular 3-wire bus is still accessible and can be
cyc
register 4 with the correct value.
pin AGCRESET. No address is needed. The sequence of the
bits is the same as described for register 6, bits 0–11. The
programming order is LSB first.
automatically parallel-load the shifted-in data bits into an internal
register. The bits will immediately effect the receiver settings.
programmed when SEN is LOW. Clock activity on SCLK will not
affect receiver gain settings when SEN is LOW.
D2
3
“FAST BUS” PROGRAMMING
D3
4
th
Min
0.5 V
–0.3
–
–
22
10
10
10
rising edge on SCLK, an internal counter will
t
r
T
setup
DD
T
D4
hold
5
Typ
–
–
10
10
100
–
–
–
t
D10
f
11
LIMITS
D11
12
Max
V
0.2 V
40
40
–
–
–
–
DD
+ 0.3
XX
A0
SA2400A
1
DD
SR02311
Product data
UNITS
UNITS
V
V
ns
ns
ns
ns
ns
ns